Semiconductor Trimmed Region Protection Against Process Damage

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Solution Overview

Problem

The trimming process in semiconductor manufacturing causes damage and pollution in the trimmed region due to structural and wafer thickness differences, leading to ineffective subsequent processes.

Innovation Solution

A semiconductor structure with a protective layer in the trimmed region is introduced, which reduces the height difference with the normal region, preventing damage from subsequent processes by covering the underlying structure and minimizing the risk of film cracking or metal loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a trimming process is conducted in semiconductor manufacturing, then the structure is modified to meet specifications, but damage and pollution occur in the trimmed region due to structural and wafer thickness differences

Engineering Contradiction:

Improvestructure specificationVSAvoiddamage and pollution in trimmed region

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

A protective layer is formed on the trimmed region before subsequent manufacturing processes. This preliminary protective action prevents damage and pollution from occurring during later steps, addressing the harmful effects caused by the trimming process while maintaining the required structural precision

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protective layer is applied specifically to the trimmed region rather than uniformly across the entire wafer. This localized approach addresses the specific damage and pollution problems in the trimmed region without unnecessarily complicating other areas, resolving the contradiction between precision modification and harmful effects

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If the top surface of the trimmed region is lower than the normal region, then the trimming specification is met, but subsequent processes cause damage due to the height difference

Engineering Contradiction:

Improvetrimmed region heightVSAvoidintegrity of structure in trimmed region

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The protective layer is deposited before subsequent manufacturing steps that could cause damage. This preliminary protection ensures that the low top surface of the trimmed region is shielded from mechanical or chemical damage during later processes, maintaining both the height specification and structural integrity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protective layer acts as a cushioning barrier that absorbs or mitigates potential damage from subsequent processes. By placing this protective barrier beforehand on the trimmed region with the lower top surface, the structure is protected from the harmful effects of height differences during manufacturing

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12094758B2Semiconductor structure and method for manufacturing the same

Publication Date: 2024.09.17 UNITED MICROELECTRONICS CORP

AI summary

A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.