Trimmed-Sample Monte Carlo Yield Analysis for IC Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional Monte Carlo simulation methods for integrated circuit design require extensive simulation time, making iterative yield-aware design flows impractical for large circuits, especially when design changes are made, due to the need for repeated simulations across numerous pseudo-random samples.
Innovation Solution
An efficient trimmed-sample Monte Carlo methodology that trims simulation samples to focus on critical samples likely to fail, allowing for preliminary yield estimation before full MC simulation, enabling designers to improve circuits sooner and reducing simulation costs through techniques like Latin Hypercube Sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional Monte Carlo simulation with pseudo-random sampling is used, then accurate yield estimation is achieved, but simulation time becomes excessively long
Solution Approach 1:
The patent performs preliminary action by sorting all pseudo-random samples based on their predicted yield contribution before simulation. Samples are arranged in descending order of expected importance, allowing the methodology to stop after processing only the critical portion of samples needed to achieve target accuracy, thus dramatically reducing simulation time while maintaining precision
Solution Approach 2:
The patent applies partial action by processing only the necessary subset of samples rather than all samples. By calculating a stopping criterion based on desired accuracy and variance, the methodology performs exactly enough simulations to achieve the target precision without unnecessary additional simulations, optimizing the balance between accuracy and time
2Reliability
If full Monte Carlo simulation is performed for every design change, then accurate yield analysis is obtained, but iterative design flow becomes impractical
Solution Approach 1:
The patent enables iterative design by performing preliminary sorting of samples once, and then reusing this sorted structure across multiple design iterations. When design changes occur, the methodology can quickly re-evaluate using the pre-established sample ordering, allowing rapid yield analysis for each iteration without repeating the full simulation process
Solution Approach 2:
The patent introduces dynamics by making the simulation process adaptive and incremental. The sorted sample structure allows the methodology to dynamically adjust the number of samples processed based on achieved accuracy, and to efficiently handle design changes by building upon previous results rather than starting from scratch
3Measurement precision
If large number of pseudo-random samples are simulated, then yield estimation accuracy improves, but computational cost increases
Solution Approach 1:
The patent applies partial action by processing only the necessary subset of samples rather than all samples. By calculating a stopping criterion based on desired accuracy and variance, the methodology performs exactly enough simulations to achieve the target precision without unnecessary additional simulations, optimizing the balance between accuracy and computational cost
Solution Approach 2:
The patent performs preliminary action by sorting all pseudo-random samples based on their predicted yield contribution before simulation. Samples are arranged in descending order of expected importance, allowing the methodology to stop after processing only the critical portion of samples needed to achieve target accuracy, thus dramatically reducing simulation time while maintaining precision
Data Source
AI summary
A method includes (a) generating a set of samples, each sample representing a respective set of semiconductor fabrication process variation values; (b) selecting a first subset of the set of samples based on a probability of the set of semiconductor fabrication process variation values corresponding to each sample; (c) estimating a yield measure for a semiconductor product based on relative sizes of the set of samples and the first subset, without performing a Monte Carlo simulation; and (d) outputting an indication that a design modification is appropriate, if the estimated yield measure is below a specification yield value.