Trimming Circuit for Semiconductor Memory Voltage Precision
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Solution Overview
Problem
Semiconductor memory apparatuses face challenges in precisely trimming internal voltages after the package process, as fuse cutting operations primarily performed at the wafer level may not accurately reflect the desired voltage levels, leading to inefficiencies in trimming internal voltages during the package level trimming process.
Innovation Solution
A trimming circuit that includes a trimming code generator capable of producing trimming code signals through addition and subtraction operations using test mode signals and fuse coding signals, and an internal voltage generator that adjusts voltages based on these signals to achieve precise trimming, with a method involving decoding fuse cutting information and generating trimming code signals to reflect the fuse cutting state in the wafer level during package-level trimming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If fuse cutting is performed at wafer level for trimming, then trimming can be done early in the manufacturing process, but the trimming precision is insufficient for package-level voltage requirements
Solution Approach 1:
The patent performs preliminary fuse cutting at wafer level to establish a base trimming state, then later performs additional code signal trimming at package level to achieve precise voltage levels. This two-stage preliminary action approach allows early process timing while maintaining final precision requirements.
Solution Approach 2:
The trimming process is segmented into two distinct stages: wafer-level fuse cutting for coarse trimming and package-level code signal adjustment for fine trimming. This segmentation allows each stage to optimize for its specific precision requirements while maintaining overall process efficiency.
2Device complexity
If only code signal trimming is used at package level, then the trimming process is simple, but the internal voltage cannot be trimmed precisely when fuse cutting was performed at wafer level
Solution Approach 1:
The patent introduces a calculator block as an intermediary component that receives both fuse cutting information and code signals, performs arithmetic operations to combine these inputs, and generates the final trimming code. This intermediary mechanism enables precise voltage trimming by mathematically integrating information from both wafer-level and package-level trimming operations.
Solution Approach 2:
The patent changes the parameter representation by encoding fuse cutting states into numerical values that can be arithmetically combined with code signal values. This parameter transformation allows the system to process and integrate information from different trimming stages using mathematical operations, achieving precise voltage control.
3Adaptability or versatility
If multiple internal voltage generators are used for different trimming targets, then various voltage levels can be generated, but the trimming control complexity increases
Solution Approach 1:
The patent implements a universal calculator block that serves multiple internal voltage generators simultaneously. This single multi-functional unit receives fuse cutting information and code signals for all voltage generators, performs the necessary arithmetic operations, and provides trimming codes to multiple targets, thereby achieving versatility without proportionally increasing control complexity.
Data Source
AI summary
A trimming circuit for a semiconductor memory apparatus includes a trimming code generator configured to provide a trimming code signal group by performing one of addition and subtraction using a test mode signal and a fuse coding signal, and an internal voltage generator configured to provide trimmed voltage in response to the trimming code signal group as output voltage.