Trimming Hard Mask Patterns for Peripheral Region CD Control
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Solution Overview
Problem
Current methods for forming gate patterns in semiconductor devices, such as DRAM, face challenges in exclusively reducing the critical dimension (CD) of the peripheral region while maintaining the CD of the cell region, as existing techniques like optical proximity correction, lithography, and etching often affect both regions simultaneously, leading to difficulties in achieving the desired CD reduction in the peripheral region.
Innovation Solution
A method involving the formation of conductive material layers, hard mask patterns, and selective etching processes is employed, where different photoresist patterns are used to define and trim hard mask layers in the cell and peripheral regions, allowing for the independent adjustment of CD in the peripheral region while maintaining uniformity in the cell region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography and etch methods are used to decrease the CD of the peripheral region, then the CD reduction is achieved, but the CD of the cell region is also affected and cannot be uniformly maintained
Solution Approach 1:
The substrate is divided into two distinct regions: cell region and peripheral region. Different photoresist patterns are applied to each region, allowing independent CD control. The cell region uses a first photoresist pattern with a first CD, while the peripheral region uses a second photoresist pattern with a second CD, enabling regional selectivity without affecting the other region.
Solution Approach 2:
Different photoresist materials or formulations are used for different regions. The first photoresist pattern for the cell region has different properties (such as different solubility, etch resistance, or pattern density) compared to the second photoresist pattern for the peripheral region, allowing each region to have optimized local characteristics for its specific function.
2Manufacturing precision
If the CD of the peripheral region is excessively decreased using conventional methods, then notching or collapse occurs
Solution Approach 1:
The critical parameters for the peripheral region are optimized independently. By using a second photoresist pattern specifically designed for the peripheral region with its unique pattern density and shape characteristics, the CD can be reduced to the desired size while maintaining pattern integrity and avoiding notching or collapse through appropriate parameter selection.
3Manufacturing precision
If OPC method is used to decrease the CD of the peripheral region, then CD reduction is achieved, but it cannot exclusively affect the peripheral region while maintaining cell region uniformity
Solution Approach 1:
The photomask process is segmented into separate exposure steps for different regions. A first photomask defines the cell region patterns with appropriate OPC, while a second photomask defines the peripheral region patterns with different OPC parameters. This segmentation allows each region to have independent CD optimization without cross-interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the selective reduction of the critical dimension in the peripheral region while maintaining the CD in the cell region, effectively supporting the fabrication of high-speed semiconductor devices by ensuring precise control over pattern dimensions.
Implementation Method 1
forming a mask pattern over the resultant structure in the cell region, exposing the peripheral region
Implementation Method 2
trimming the hard mask patterns in the peripheral region
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a conductive material layer for forming a gate over a substrate including a cell region and a peripheral region, forming hard mask patterns over the conductive material layer, forming a mask pattern over the resultant structure in the cell region, exposing the peripheral region, trimming the hard mask patterns in the peripheral region, removing the mask pattern, and etching the conductive material layer to form gate patterns using the hard mask patterns.