Trip Logger Circuitry for Cascaded Fault Sequence Detection
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Solution Overview
Problem
Existing circuits fail to capture the sequence and timing of trip events, making it difficult to determine the root cause of failures, especially in complex systems like enhanced pulse width modulation (ePWM) circuits, where multiple faults can occur from both internal and external stimuli.
Innovation Solution
The implementation of trip logger circuitry that monitors trip sources, detects trip events, and records their sequence and timing using counters and memory structures, allowing for the storage of event information to analyze fault origins and restore systems effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If trip logger circuitry is implemented to capture sequence and timing of trip events, then diagnostic capability is improved, but device complexity increases
Solution Approach 1:
The trip logger circuitry is integrated within the existing ePWM circuit architecture, nesting the diagnostic functionality inside the controller. The event memory and counters are incorporated as internal components of the trip logger module, which itself is part of the ePWM controller, creating a hierarchical nested structure that minimizes external complexity while maintaining precise trip event capture capability
Solution Approach 2:
The trip logger circuitry acts as an intermediary component between the trip sources (fault detection points) and the diagnostic system. It captures trip events from multiple sources, records their sequence and timing in the event memory, and provides this structured information to external diagnostic interfaces, thereby improving measurement precision without requiring direct complex connections between all trip sources and the diagnostic system
2Reliability
If multiple trip sources are monitored simultaneously, then reliability is improved, but device complexity increases
Solution Approach 1:
The trip logger circuitry is designed with universal monitoring capability that can track multiple different trip sources (overcurrent, undervoltage, thermal, etc.) using the same core event capture mechanism. The event memory structure and counter system serve multiple functions: recording trip sequence, timing information, and source identification simultaneously, thereby improving reliability through comprehensive monitoring without proportionally increasing circuit complexity
Solution Approach 2:
The monitoring system is segmented into distinct functional modules: trip source inputs, event detection logic, counter units for timing, and event memory for storage. Each segment handles a specific aspect of trip event capture, allowing the system to monitor multiple trip sources reliably while keeping each individual module relatively simple and manageable
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods are disclosed for real-time trip sequence detection for cascaded trip events. An example integrated circuit device includes trip detector circuitry, a first counter, a first memory, a second counter, a second memory, and control circuitry in communication with the trip detector circuitry, the control circuitry to, in response to a first trigger detected by the fault detector circuit, store a value of the first counter in the first memory, and in response to a second trigger detected by the fault detector circuit, store a value of the second counter in the second memory. The trip detector circuitry will continue the same detection, identification and counter storage logic for the subsequent triggers limited only by the available storage capacity.