Tri-State Node Fault Detection via Pull-Up Transistor Activation
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Solution Overview
Problem
Existing IC testing methods, such as broadside and internal scan testing, do not adequately diagnose faults in tri-state nodes and test chains, and the additional circuitry required for internal scan testability can introduce functional problems that need to be tested as well.
Innovation Solution
A system that uses a test chain with a pull-up transistor to activate tri-state nodes during testing, allowing for the detection of faults in one-hot transmission-gate multiplexers and test chains by propagating test signals through buffers and storing output in registers, enabling identification of stuck-at faults and opens.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If internal scan testing is used to test interconnections and transistors, then testability is improved, but additional circuitry is added that may introduce functional problems
Solution Approach 1:
A test chain is introduced as an intermediary component between the test system and the IC under test. The test chain includes test cells connected to pins, buffers for signal propagation, and registers for data storage, enabling comprehensive testing of interconnections and transistors without directly modifying the core IC functionality.
Solution Approach 2:
The testing system is segmented into distinct functional components: test cells for pin control, buffers for signal transmission, and registers for data capture. This segmentation allows each component to be independently tested and optimized, improving overall testability while managing complexity through modular design.
2Difficulty of detecting and measuring
If test cells are added to override pin functionality for internal scan testing, then diagnostic capability is improved, but the test chain itself requires testing
Solution Approach 1:
The test chain is designed to be self-testable through the inclusion of pull-up transistors connected to test nodes. These pull-up transistors can be activated during testing to force known logic states, enabling the test chain to diagnose its own functionality and distinguish between faults in the test chain versus faults in the device under test.
Solution Approach 2:
The system incorporates feedback mechanisms where test results from the IC are captured by registers and fed back to the test system for analysis. This feedback loop enables comprehensive diagnostic capability, allowing the system to determine whether faults originate from the IC or the test chain itself.
3Measurement precision
If pull-up transistors are added to test tri-state nodes, then fault detection capability is improved, but circuit complexity increases
Solution Approach 1:
Pull-up transistors are added selectively at specific test nodes where tri-state functionality needs to be tested, rather than throughout the entire circuit. This localized approach enables precise fault detection at critical points while minimizing the overall increase in circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively detects faults in tri-state nodes and test chains, distinguishing between faults in the multiplexers and test chains, thereby improving diagnostic accuracy and ensuring the reliability of IC testing.
Implementation Method 1
a pull-up transistor may be added to the one-hot transmission-gate multiplexer. During normal operation of the one-hot transmission-gate multiplexer the added pull-up transistor is inactivated. However, when testing a tri-state node in the one-hot transmission-gate multiplexer, the pull-up transistor is activated to weakly pull the tri-stated node to a high logical value
Data Source
AI summary
An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.