Triple Adder Circuit for Sum Plus One and Two Generation
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Solution Overview
Problem
Existing data processing systems require significant circuit space and power to calculate the sum of two operands and their subsequent increments (sum+1 and sum+2), either using multiple adder circuits in parallel or series, which are inefficient in terms of speed and power consumption.
Innovation Solution
A data processing apparatus and method that uses addition circuitry to produce intermediate data during the calculation of a sum, which is then used to simultaneously calculate the sum, sum+1, and sum+2 within a single clock cycle, reducing circuit size and power consumption by avoiding the need for multiple adder circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If three adder circuits are used in parallel to calculate sum, sum+1, and sum+2, then calculation speed is improved, but circuit space and power consumption increase significantly
Solution Approach 1:
The patent merges the functionality of three separate adder circuits into a single adder circuit by reusing the same hardware resources. The adder circuit performs multiple addition operations (A+B, A+B+1, A+B+2) sequentially within one clock cycle, eliminating the need for three separate adders and thereby reducing circuit space while maintaining calculation speed.
Solution Approach 2:
The single adder circuit is designed to perform multiple functions: it calculates A+B, then A+B+1, and finally A+B+2 within one clock cycle. This multi-functional approach allows one circuit to replace three dedicated adders, reducing overall circuit space while maintaining the ability to produce all three sums simultaneously.
2Area of stationary object
If one or more dual adder circuits are used in series to calculate sum, sum+1, and sum+2, then circuit space is reduced, but calculation speed decreases
Solution Approach 1:
The adder circuit performs preliminary calculations of A+B first, then uses this result as a base for subsequent calculations of A+B+1 and A+B+2. By preparing the intermediate result A+B in advance within the same clock cycle, the circuit avoids sequential processing delays that would occur with traditional series adder configurations, thereby maintaining high speed while using minimal circuit space.
Solution Approach 2:
The adder circuit maintains continuous useful action by seamlessly transitioning from calculating A+B to A+B+1 to A+B+2 without idle periods. The output of one addition operation immediately becomes the input for the next, ensuring that the circuit remains productive throughout the entire clock cycle and achieving both space efficiency and high speed.
3Productivity
If multiple adder circuits are used to calculate sum, sum+1, and sum+2, then all values can be produced in one clock cycle, but power consumption increases
Solution Approach 1:
The patent combines the power-consuming resources of three separate adder circuits into a single adder circuit. By reusing the same hardware components for multiple calculation tasks within one clock cycle, the system achieves high productivity while significantly reducing power consumption compared to having three independent adders operating simultaneously.
Solution Approach 2:
The adder circuit serves itself by reusing its own output as input for subsequent calculations. After calculating A+B, the circuit immediately uses this result to calculate A+B+1 and then A+B+2, eliminating the need for separate dedicated circuits. This self-service approach reduces overall power consumption while maintaining the ability to produce all three values in one clock cycle.
Data Source
AI summary
A data processing apparatus is provided, which includes addition circuitry that performs a calculation of a sum of a first operand and a second operand. The addition circuitry produces an intermediate data prior to the calculation completing. Determination circuitry uses the intermediate data to produce the sum of the first operand and the second operand plus 1. Further determination circuitry configured to use the intermediate data to produce the sum of the first operand and the second operand plus 2.