Triple Buffer Data Transfer Control for Sequential Image Streams

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Solution Overview

Problem

Conventional data transfer control devices with a triple-buffer configuration often discard or overwrite non-referenced data, leading to data loss and inefficiencies in transferring large amounts of data, especially for real-time applications like moving images.

Innovation Solution

A data transfer control device with a physical buffer divided into three buffers, where selectors determine the read and write buffers based on the state of the intermediate buffer and write operation, ensuring data is transferred sequentially and minimizing buffer switching operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the buffer switching algorithm prioritizes the most recent data, then the data supply speed is improved, but non-referenced data is discarded leading to data loss

Engineering Contradiction:
Improvedata supply speedVSAvoiddata loss
Core Design Contradiction:
SpeedVSLoss of information

Solution Approach 1:

The physical buffer is divided into three separate buffers: a write buffer for receiving new data, a read buffer for supplying data to the data reference unit, and a storage buffer for holding non-referenced data. This segmentation allows the system to maintain multiple data states simultaneously, preventing data loss while enabling fast data supply by selectively switching between buffers based on actual reference needs.

Inventive Principle:
Principle #1Segmentation

2Speed

If buffer switching operations are performed frequently to supply the most recent data, then the data transfer speed is improved, but the buffer control complexity increases

Engineering Contradiction:
Improvedata transfer speedVSAvoidbuffer control complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The buffer control device dynamically adjusts buffer allocation based on real-time conditions. When data in the write buffer is referenced, the system automatically switches the read buffer to the storage buffer, which contains non-referenced data ready for immediate supply. This dynamic adaptation eliminates unnecessary buffer switching operations while maintaining fast data transfer, reducing control complexity through condition-based automation.

Inventive Principle:
Principle #15Dynamics

3Loss of information

If the storage buffer is used to hold non-referenced data, then data loss is prevented, but the device complexity increases

Engineering Contradiction:
Improvedata loss preventionVSAvoiddevice complexity
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The storage buffer serves multiple functions: it holds non-referenced data from the write buffer, provides data for supply to the data reference unit, and acts as a backup buffer during switching operations. By making the storage buffer multi-functional, the system prevents data loss without proportionally increasing device complexity, as the same physical resource performs multiple protective and operational roles.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7657673B2Data transfer control device, image processing device, and data transfer control method
Publication Date: 2010.02.02 RENESAS ELECTRONICS CORP
  • US7657673B2 patent drawing
  • US7657673B2 patent drawing
  • US7657673B2 patent drawing

AI summary

A data transfer control device, which transfers a large capacity of data speedily and sequentially, has three buffers that are used as a WR (write) buffer, an intermediate buffer, and an RD (read) buffer. To send data sequentially, the data transfer control device switches-over the buffers in one of the following three ways (A), (B), and (C), using determination flags indicating whether the buffers store effective data (data not yet referenced). A buffer control device switches-over (A) the WR buffer and RD buffer if a WR buffer effective flag 33 is on and an intermediate buffer effective flag 34 and an RD buffer effective flag 35 are off, (B) the WR buffer and the intermediate buffer if the WR buffer effective flag 33 and the RD buffer effective flag 35 are on and the intermediate buffer effective flag 34 is off, and (C) the intermediate buffer and the RD buffer if the intermediate buffer effective flag 34 is on and the RD buffer effective flag 35 is off.