Triple-DAC SAR ADC for Reduced Switching Wait Time
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Solution Overview
Problem
High-resolution SAR ADCs face efficiency issues due to the long switching time of digital-to-analog converters (DACs) during the conversion process, which affects the overall conversion efficiency.
Innovation Solution
The SAR ADC employs a DAC array with three DACs and three comparators, where the SAR logic circuit strategically chooses a comparator and adjusts the sampling results of the other DACs to reduce waiting time for DAC switching, thereby improving conversion efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single DAC is used in the SAR ADC, then the device complexity is low, but the conversion efficiency deteriorates due to long switching time
Solution Approach 1:
The patent divides the DAC function into three separate DAC units (first DAC, second DAC, third DAC), each handling different bit positions of the conversion. This segmentation allows parallel operation where one DAC can be switched while others continue comparing, thereby resolving the contradiction between conversion efficiency and device complexity by enabling concurrent operations across multiple DAC segments.
Solution Approach 2:
The patent implements preliminary action by pre-adjusting the sampling results of the second and third DACs to voltage levels corresponding to possible nth bit values (0 or 1) before the comparison stage. This allows the SAR ADC to immediately use these pre-prepared DAC outputs without waiting for switching during the comparison phase, thus improving conversion efficiency while maintaining manageable device complexity.
2Measurement precision
If more bits of digital signal are converted, then the resolution is improved, but the total switching time of DAC increases
Solution Approach 1:
By segmenting the DAC into three units that handle different bit positions, the patent enables simultaneous comparison operations for multiple bits. This allows high-resolution conversion (more bits) without proportionally increasing total switching time, as multiple DAC segments operate in parallel rather than sequentially.
Solution Approach 2:
The patent maintains continuity of useful action by ensuring that while one DAC is being switched, the other two DACs continue performing comparison operations without interruption. This continuous operation across multiple DAC units allows more bits to be converted without increasing the overall conversion time, thereby improving resolution without proportional time penalty.
3Speed
If the SAR ADC waits for DAC switching between comparison stages, then the conversion accuracy is maintained, but the conversion speed deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the sampling results of unused DACs (second and third DACs) to voltage levels corresponding to both possible values of the nth bit (0 or 1) before the comparison stage. This ensures that when the comparison is complete, the next DAC can immediately switch to the required voltage level without waiting, maintaining conversion accuracy while significantly improving conversion speed.
Solution Approach 2:
The patent implements dynamics by making the DAC array highly adaptable and reconfigurable. The SAR logic circuit dynamically selects which DAC to use for each comparison stage and pre-adjusts the sampling results of other DACs based on the current conversion state. This dynamic adaptation allows the system to maintain accurate comparisons while minimizing switching wait time, thereby improving conversion speed without sacrificing reliability.
Data Source
AI summary
A SAR ADC is configured to receive an input signal and comprises a DAC array and a SAR logic circuit coupled to each other. The DAC array comprises three DACs sampling an input voltage level of input signal and three comparators respectively connected in series with three DACs for generating a comparison result. The SAR logic circuit generates nth bit of a conversion result according to comparison result in nth comparison stage. In nth comparison stage, SAR logic circuit chooses a first comparator to compare a sampling result of a first DAC with voltage level corresponding to the first (n-1) bits of conversion result, according to comparison result of (n-1)th comparison stage, to generate comparison result, and adjusts sampling results of second and third DACs corresponding to second and third comparators to voltage levels respectively corresponding to cases where the nth bit of conversion result is 0 and 1.