Triple-DC-Port Half-Bridge Module for Low-Inductance Switching
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Solution Overview
Problem
Inverters in high voltage applications, such as electric vehicles, face challenges with parasitic inductances that increase heat and reduce performance due to commutation cell inductance (CCL), limiting switching speeds and causing power losses.
Innovation Solution
The inverter design includes a power module with symmetrical current paths and metal spacers between substrate layers, utilizing three DC power tabs instead of two, to reduce parasitic inductances and improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional two DC port half-bridge inverter design is used, then device complexity is reduced, but parasitic inductances increase causing higher commutation cell losses
Solution Approach 1:
The single negative DC power tab is segmented into two separate negative DC power tabs (first negative DC power tab and second negative DC power tab), each connected to different groups of phase switches. This segmentation creates separate current paths that reduce parasitic inductances and commutation cell losses while maintaining the basic two-port half-bridge structure.
Solution Approach 2:
The patent transitions from a planar two-port configuration to a three-dimensional multi-layer substrate architecture with three DC power tabs distributed across different layers. The first and second negative DC power tabs are on a first substrate, while the positive DC power tab is on a second substrate, creating vertical current paths that reduce parasitic inductance.
2Speed
If longer current paths are used to connect DC power tabs to phase switches, then connectivity is improved, but parasitic inductances increase reducing switching speed
Solution Approach 1:
The patent uses multi-layer substrate architecture with vertical connections via vias and conductive structures to create three-dimensional current paths. This reduces the horizontal trace length on each layer while maintaining electrical connectivity, thereby reducing parasitic inductance and enabling higher switching speeds.
Solution Approach 2:
The patent introduces intermediate connection structures including vias, conductive pads, and metal traces that serve as mediators between DC power tabs and phase switches. These intermediaries provide low-inductance pathways that minimize power losses while maintaining proper electrical connections.
3Reliability
If asymmetric arrangement of phase switches is used, then ease of manufacture is improved, but commutation cell inductance increases reducing performance
Solution Approach 1:
While maintaining overall symmetrical current paths, the patent allows for asymmetric placement of phase switches within each group (first group connected to first negative DC power tab, second group connected to second negative DC power tab). This enables optimization for manufacturing while preserving the symmetrical current distribution that minimizes commutation cell inductance.
Solution Approach 2:
The patent applies different local arrangements to different groups of phase switches, where each group can be optimized independently for manufacturing while maintaining the overall symmetrical current path structure. This allows local asymmetries that facilitate manufacturing without compromising the global performance characteristics.
Data Source
AI summary
Disclosed solutions relate to electrical inverters. An inverter may further include may include a power module including phase switches, a first negative DC power tab, and a second negative DC power tab. The first negative DC power tab and the second negative DC power tab are connected to one or more of the phase switches. The inverter may further include a positive DC power tab positioned between the first negative DC power tab and the second negative DC power tab and connected to the phase switches. The inverter may further include one or more phase AC power tabs to receive AC power from the phase switches.