Triple-Diagonal LDPC Parity Matrix for Low-Complexity Error Correction
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Solution Overview
Problem
Existing data transmission technologies face challenges in efficiently correcting errors over noisy media due to the complexity and cost of implementing error correction codes, particularly with low density parity check codes, which often require large parity matrices for optimal performance.
Innovation Solution
A method and device for data transmission using a quasi-cyclic Low Density Parity Check (LDPC) code with a unique parity matrix structure featuring a triple diagonal section, reducing the number of columns with a Hamming weight less than or equal to 2, while maintaining low implementation complexity, and incorporating a puncturing technique to adjust redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low density parity check codes are used for error correction, then error correction capability is improved, but implementation complexity and cost increase
Solution Approach 1:
The patent changes the structural parameters of the parity matrix by introducing a triple diagonal structure with specific constraints on column Hamming weights. This structural parameter change enables better error correction performance while reducing implementation complexity compared to conventional LDPC codes
Solution Approach 2:
The patent applies local quality by creating different structural characteristics in different parts of the parity matrix. The triple diagonal structure with controlled Hamming weights creates localized patterns that optimize both error correction capability and implementation efficiency in specific regions of the code
2Reliability
If large parity matrices are used for optimal error correction performance, then error correction capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent changes the dimensional parameters of the parity matrix by enforcing a triple diagonal structure with limited non-zero elements per column. This parameter change reduces the effective size and complexity of the parity matrix while maintaining optimal error correction performance through the structured design
3Reliability
If redundancy is increased for better error correction, then error correction capability is improved, but data transmission efficiency decreases
Solution Approach 1:
The patent optimizes the redundancy parameter by carefully controlling the Hamming weights in the triple diagonal structure. This parameter optimization achieves the minimum necessary redundancy for effective error correction while maximizing data transmission efficiency by avoiding excessive parity bits
Data Source
AI summary
A method including generating a matrix. The matrix includes first and second portions. The first portion includes data bits. The second portion includes parity bits and has a triple diagonal structure. The triple diagonal structure includes a first central diagonal, a second central diagonal, and a last row diagonal. Bits of the first central diagonal, the second central diagonal, and the last row diagonal are equal to 1 and a remainder of bits in the triple diagonal structure are equal to 0. The method further includes: determining parity bits based on the matrix; if the matrix is generated to codify data for transmission from a first device to a second device, transmitting the parity bits from the first device to the second device; and if the matrix is generated based on a vector of bits received from the second device, generating a block of data based on the parity bits.