Triple-DLL Clock Voting With Phase Compensation for Soft Error Tolerance
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Solution Overview
Problem
Existing ICs face challenges in achieving robust fault and soft error tolerance in clock subsystems, particularly in delay-locked loops, which are crucial for clock synchronization across heterogeneous integration of functional dies with different processing technologies.
Innovation Solution
The implementation of three delay-locked loops and three dummy voter circuits, along with a voter circuit that compensates for phase differences, ensures synchronization of the output clock signal with the reference clock signal by using NAND gates to combine intermediate clock signals and generate an output clock signal only when more than two signals are logic high, thereby filtering out false statuses and phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single delay-locked loop is used for clock synchronization, then the device complexity is low, but the reliability is insufficient against faults and soft errors
Solution Approach 1:
The system divides the clock synchronization function into three separate delay-locked loops (DLL0, DLL1, DLL2) that operate independently. Each DLL processes the reference clock signal separately and produces an intermediate clock signal, allowing individual fault isolation and maintaining overall system reliability through functional segmentation.
Solution Approach 2:
Each delay-locked loop is assigned a specific local function with dedicated dummy voter circuits that compensate for phase delays specific to that loop's path. The voter circuit then performs local majority voting on the intermediate clock signals to produce the final output clock signal, ensuring that local phase errors do not propagate system-wide.
2Measurement precision
If intermediate clock signals are directly combined without phase compensation, then the device complexity is low, but the synchronization precision deteriorates due to phase delays
Solution Approach 1:
The dummy voter circuits are positioned before the main voter circuit to pre-compensate for phase delays in each intermediate clock signal path. By advancing the phase of each intermediate clock signal through its corresponding dummy voter circuit, the signals arrive at the voter circuit with corrected timing, enabling precise synchronization without requiring complex post-compensation mechanisms.
3Reliability
If all intermediate clock signals are used to generate output clock signal, then the productivity is high, but the reliability decreases when soft errors occur
Solution Approach 1:
The voter circuit implements a majority voting mechanism that continuously monitors the logic states of three intermediate clock signals and generates the output clock signal based on the majority state. This feedback-based voting process automatically filters out soft errors that cause transient incorrect states in individual intermediate signals, as the majority vote will correct isolated errors without requiring retransmission or regeneration.
Data Source
AI summary
An electronic device includes three delay-locked loops, three dummy voter circuits, and a voter circuit. Each of the three delay-locked loops has a first input end, a second input end, an output end to maintain the phase difference between the reference clock signal received from the first input end and the intermediate clock signal output from the output end. Each of the three voter circuits is connected between the second input end and the output end of each of the three delay-locked loops to delay the phase of the intermediate clock signal by the phase difference. The voter circuit receives the intermediate clock signal from each of the three delay-locked loops, and outputs an output clock signal according to the logic of the intermediate clock signal from each of the three delay-locked loops. The phase difference compensates for the phase delay of the intermediate clock signal passing through the voter circuit.