Triple Exposure Lithography for Hexagonal Memory Pillar Arrays
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Solution Overview
Problem
Conventional lithography techniques, such as double exposure, are unable to effectively reduce the half-pitch of memory array layouts, limiting the miniaturization of memory devices and increasing die area requirements.
Innovation Solution
The implementation of triple or quadruple exposure techniques using multiple masks to pattern photoresist layers, allowing for the formation of pillar-shaped devices in a hexagonal or grid pattern, which enables smaller half-pitches and reduced die sizes by relaxing the array pattern configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If double exposure technique is used to reduce half-pitch, then the half-pitch of bit and word lines can be reduced by a factor of 2, but the spacing of memory cell layout can only be reduced by a factor of 1.4
Solution Approach 1:
The patent segments the patterning process into multiple discrete exposure steps (triple or quadruple exposure) with separate masks, allowing independent optimization of different feature sets. This enables the bit/word line spacing and memory cell spacing to be reduced by different factors, resolving the limitation where both dimensions were constrained by the same 1.4x reduction factor.
Solution Approach 2:
The patent transitions from conventional rectangular (Cartesian) grid layout to a hexagonal lattice layout. This geometric transformation allows for more efficient space utilization and enables greater reduction in minimum spacing between features. The hexagonal arrangement provides six-fold symmetry that accommodates the multiple exposure patterns more effectively, achieving superior density compared to the rectangular grid.
2Ease of manufacture
If conventional rectangular layout is used, then the array structure is logical and simple, but the half-pitch cannot be effectively reduced with double exposure techniques
Solution Approach 1:
The patent introduces asymmetry in the exposure pattern arrangement by using hexagonal symmetry instead of rectangular symmetry. The hexagonal lattice allows for non-orthogonal arrangements of exposed regions that cannot be achieved with conventional rectangular masks, enabling more aggressive half-pitch reduction while maintaining manufacturability through systematic pattern generation.
Solution Approach 2:
By changing from rectangular to hexagonal geometry, the patent accesses a different dimensional arrangement of features. The hexagonal lattice provides alternative spatial relationships between adjacent features, allowing for reduced minimum distances while maintaining logical array structure through the systematic repetition of the hexagonal unit cell.
3Area of stationary object
If triple or quadruple exposure is used to form hexagonal pattern, then smaller half-pitches and reduced die sizes are achieved, but the process complexity increases
Solution Approach 1:
The patent merges multiple exposure patterns into a single hexagonal lattice structure. By carefully designing the relative positions and orientations of the multiple exposure fields, the complex multi-step process produces a unified, regular hexagonal pattern that can be systematically generated and aligned, reducing the practical complexity compared to forming irregular patterns through multiple steps.
Solution Approach 2:
The patent employs periodic action through the repeated application of exposure steps at regular intervals and orientations. The hexagonal lattice is generated by periodic repetition of the exposure pattern in six-fold symmetry, allowing for predictable and systematic process control. This periodicity simplifies alignment and reduces variability compared to aperiodic multi-step patterning approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of memory devices with smaller half-pitches, reducing die area requirements and enabling more efficient use of reduced scaling factors, while maintaining or improving the density of memory cell packing.
Implementation Method 1
A first exposure of the photoresist layer is performed using a first mask to form first exposed regions in the photoresist layer. A second exposure of the photoresist layer is performed using a second mask to form second exposed regions in the photoresist layer.
Data Source
AI summary
Methods of making pillar shaped device array using a triple or quadruple exposure technique are described. A plurality of pillar shaped devices are formed arranged in a hexagonal or rectangular pattern.