Triple Gate Oxide Thickness Integration Divot Reduction
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Solution Overview
Problem
The formation of divots in shallow trench isolation (STI) structures during oxide removal processes for triple gate oxide (TGO) chips increases sub-threshold leakage current, particularly in low voltage regions, due to the differing etch rates at peripheral edges.
Innovation Solution
A method is developed to form TGO chips by creating regions with different gate oxide thicknesses, where an intermediate thickness gate oxide layer is formed and selectively removed, followed by the growth of thin and thick gate oxide layers, and deposition of conductive layers, reducing divot formation through controlled masking and etching steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If oxide removal processes are performed to form different gate oxide thicknesses, then triple gate oxide chips can be manufactured, but divots are formed in STI structures increasing sub-threshold leakage current
Solution Approach 1:
The oxide removal process is segmented into multiple selective steps: first removing oxide from low voltage regions, then from intermediate voltage regions, while preserving oxide in high voltage regions. This segmentation allows different gate oxide thicknesses to be formed without excessive divot formation in STI structures, as each removal step is controlled and targeted.
Solution Approach 2:
Different gate oxide thicknesses are created in different regions of the chip according to local requirements: thin gate oxide in low voltage regions, intermediate thickness in medium voltage regions, and thick gate oxide in high voltage regions. This local quality approach ensures each region has the optimal oxide thickness for its operating voltage while minimizing harmful divot effects through controlled selective removal.
2Adaptability or versatility
If multiple oxide removal and growth steps are performed, then different gate oxide thicknesses are achieved, but manufacturing process complexity increases
Solution Approach 1:
A preliminary intermediate thickness gate oxide layer is formed across all regions before selective removal. This preliminary action establishes a uniform base layer that can be selectively removed in subsequent steps, simplifying the overall process by ensuring consistent starting conditions for all regions and reducing the need for multiple growth cycles.
Solution Approach 2:
The manufacturing process maintains continuity by performing oxide removal and conductive layer deposition in an integrated sequence without interrupting the production flow. The selective oxide removal is followed immediately by conductive layer formation in the same process cycle, maintaining continuous useful action while achieving the required gate oxide thickness variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces divot formation in STI structures, thereby minimizing sub-threshold leakage current, especially in low voltage areas, without adding excessive complexity to the manufacturing process.
Implementation Method 1
an intermediate thickness gate oxide layer is formed over regions of the first kind, second kind and third kind
Implementation Method 2
removed from regions of the first kind where a thin gate oxide layer is grown
Data Source
AI summary
A method for forming TGO structures includes providing a substrate containing regions of first, second and third kinds in which devices with respective first, second and third gate oxide layers of different thicknesses are to be formed. The second gate oxide layer is formed over the substrate and then removed from regions of the first kind where the first gate oxide layer is subsequently grown. A first conductive layer is deposited over the substrate. The first conductive layer and second gate oxide layer are subsequently removed from regions of the third kind. The third gate oxide layer followed by deposition of a second conductive layer is formed over the substrate and then removed except from over regions of the third kind.