Triple Gate Oxide FinFET for Multi-Voltage Integration
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Solution Overview
Problem
Conventional transistors face challenges in controlling current flow as transistor size decreases, and high-k metal gate (HKMG) transistors offer limited gate oxide thickness levels, insufficient for supporting multiple voltage levels required in integrated circuit devices.
Innovation Solution
The development of FinFET integrated circuits with triple gate oxide devices, where polysilicon and metal gate transistors are formed with multiple levels of oxide thicknesses to enable better voltage control, including the fabrication of polysilicon gate structures over fin-shaped channel structures and deposition of high-k dielectric material followed by a metal layer to create high-k metal gate transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If HKMG transistors are used to reduce current leakage, then current leakage is reduced, but the number of gate oxide thickness levels is limited to two
Solution Approach 1:
The gate structure is segmented into two distinct types: polysilicon gate structures and metal gate structures. Each segment serves a specific voltage level requirement, allowing the integrated circuit to support multiple voltage levels (low, medium, high) while maintaining the benefits of HKMG transistors for current leakage reduction.
Solution Approach 2:
Different regions of the integrated circuit are assigned different gate structures based on their voltage level requirements. Low voltage devices use thin oxide with polysilicon or metal gates, medium voltage devices use medium thickness oxide, and high voltage devices use thick oxide. This local differentiation enables triple gate oxide functionality throughout the circuit.
2Productivity
If transistor size is reduced to pack more transistors on a single chip, then transistor density increases, but gate control over current flow deteriorates
Solution Approach 1:
The gate structure transitions from a planar configuration to a three-dimensional FinFET configuration where the gate wraps around the fin structure. This curved/gated-around configuration provides superior electrostatic control over the channel, enabling effective gate control even as transistor dimensions are reduced to increase density.
3Adaptability or versatility
If polysilicon gate structures are used to support multiple voltage levels, then voltage control flexibility is improved, but current leakage increases
Solution Approach 1:
The gate structure is segmented into two distinct types: polysilicon gate structures and metal gate structures. Each segment serves a specific voltage level requirement, allowing the integrated circuit to support multiple voltage levels (low, medium, high) while maintaining the benefits of HKMG transistors for current leakage reduction.
Solution Approach 2:
The gate structure uses composite materials combining polysilicon and metal layers with high-k dielectric material. This composite structure enables the gate to function effectively across multiple voltage levels while the high-k dielectric provides superior electrical insulation to reduce current leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved voltage control and reduced current leakage, enabling the integration of transistors with three levels of oxide thicknesses, supporting multiple voltage levels in integrated circuit devices.
Implementation Method 1
A layer of high-k dielectric material is deposited on the exposed surface region of that fin-shaped channel structure
Implementation Method 2
a metal layer may then be deposited over the high-k dielectric material to form a high-k metal gate transistor
Data Source
AI summary
A method of fabricating an integrated circuit includes forming a plurality of polysilicon gate electrode structures over a plurality of fin-shaped channel structures. A portion of the plurality of polysilicon gate electrode structures may then be removed to expose a surface region of a fin-shaped channel structure in the plurality of fin-shaped channel structures. The remaining portion of the polysilicon gate electrode structures may form a plurality of polysilicon transistors. A layer of high-k dielectric material is deposited on the exposed surface region of the fin-shaped channel structure. A metal layer may be deposited over the high-k dielectric material to form at least one high-k metal gate transistor over the fin-shaped channel structure.