Triple-Gate Oxide-Silicon TFT for Variable Refresh Rate Displays
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Solution Overview
Problem
Current display technologies face challenges in achieving high resolution while reducing power consumption and preventing brightness deviations during variable frequency driving, which affects display quality and refresh rates.
Innovation Solution
The display apparatus incorporates a substrate with specific thin-film transistors, including silicon and oxide semiconductor layers, and a unique capacitor structure to optimize signal transmission and voltage initialization, ensuring efficient power use and reduced brightness deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a display apparatus uses conventional transistor structures with single gate electrodes, then the device complexity is low, but the manufacturing precision and display resolution are insufficient
Solution Approach 1:
The patent introduces a third gate electrode positioned below the semiconductor layer, adding a vertical dimension to the gate control structure. This triple-gate configuration (first gate above, second gate beside, third gate below) enables precise control of the semiconductor layer from multiple spatial directions, significantly improving manufacturing precision and display resolution while managing device complexity through systematic structural organization
Solution Approach 2:
The gate control function is segmented into three independent gate electrodes positioned at different locations relative to the semiconductor layer. This segmentation allows each gate to independently control different aspects of the semiconductor channel, enabling fine-tuned precision control for high-resolution display manufacturing
2Productivity
If the display apparatus uses high refresh rates, then the display quality improves, but the power consumption increases
Solution Approach 1:
The patent implements dynamic control of the semiconductor layer through multiple independently controllable gates, allowing the display to adapt its electrical characteristics in real-time. This dynamic control enables efficient power management during variable refresh rate operation, maintaining high display quality at high refresh rates while reducing power consumption during lower refresh rate operations
Solution Approach 2:
The triple-gate structure enables independent adjustment of electrical parameters such as threshold voltage and channel conductivity. By dynamically changing these parameters based on refresh rate requirements, the display can optimize power consumption while maintaining image quality across different operating conditions
3Adaptability or versatility
If the display apparatus uses variable refresh rate driving, then the adaptability improves, but brightness deviations occur
Solution Approach 1:
The multiple gate electrodes enable feedback control mechanisms where the electrical state of the semiconductor layer can be monitored and adjusted through the gates. This feedback capability ensures consistent brightness across variable refresh rates by compensating for any deviations that occur during different operating conditions
Solution Approach 2:
The patent structures the gate electrodes to maintain uniform electrical potential distribution across the semiconductor layer during operation. This equipotential design ensures that brightness remains consistent across different refresh rates by preventing potential differences that would cause brightness deviations
Data Source
AI summary
A display apparatus includes a substrate, a scan line disposed over the substrate and extending in a first direction, an initialization voltage line disposed over the substrate and extending in the first direction, a first thin-film transistor including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, the first semiconductor layer including a silicon semiconductor, and a second thin-film transistor including a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer including an oxide semiconductor, wherein the second semiconductor layer is disposed between the scan line and the initialization voltage line in a plan view, and the second gate electrode extends from the scan line in a second direction perpendicular to the first direction.