Triple-Gate Logic Memory Cell for Ternary Computing and Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional logic memory technologies face challenges in implementing ternary logic operations, memory functions, and integration limitations due to the separation of processor and memory, high power consumption, and reliance on non-silicon materials, which complicates commercialization and limits integration and reliability.
Innovation Solution
A universal logic memory cell using a triple-gate silicon device with a positive feedback loop, capable of performing ternary logic operations and memory functions, is developed using a conventional CMOS process, allowing for all basic logic operations in a single structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional logic memory technology uses volatile memory devices such as SRAM and DRAM, then memory function is achieved, but a large number of transistors are required which limits overall area and power consumption
Solution Approach 1:
The patent combines computational logic functions and memory storage functions into a single integrated cell structure. The logic memory cell performs both logic operations (AND, OR, NOT, NAND, NOR, XOR) and stores ternary logic values (0, 1, 2) using the same physical components, eliminating the need for separate transistor arrays for memory while maintaining stable memory function through the inherent state retention of the logic circuit.
Solution Approach 2:
The logic memory cell is designed as a universal structure that can perform multiple logic operations and store memory values using the same cell configuration. By controlling the input signals and feedback mechanisms, the same physical cell can execute different logic functions and retain ternary states, reducing the overall transistor count while maintaining functional reliability.
2Reliability
If logic memory technology uses nonvolatile memory devices such as ReRAM, MRAM, and PCRAM, then memory function is achieved, but complex non-silicon material processes are required which reduce device uniformity and stability
Solution Approach 1:
The patent uses uniform silicon-based CMOS technology throughout the logic memory cell structure, eliminating the need for heterogeneous non-silicon materials. All transistors and circuit components are fabricated using standard silicon processing techniques, ensuring device uniformity, stability, and compatibility with existing manufacturing processes while achieving both logic and memory functions.
3Ease of operation
If conventional logic memory technology separates processor and memory functions, then individual circuit optimization is possible, but data transmission time and latency increase due to physical separation
Solution Approach 1:
The patent merges the processor (logic) and memory functions into a single logic memory cell that performs both computational and storage operations. The cell uses feedback loops and state retention mechanisms to maintain memory values while simultaneously executing logic operations, eliminating the need for data transmission between separate processor and memory units and thereby reducing latency and transmission time.
4Quantity of substance
If multiple-valued logic systems are used to overcome information density limitations, then information density is improved, but power consumption increases due to leakage current
Solution Approach 1:
The patent implements ternary logic (three-valued logic with states 0, 1, 2) by utilizing the natural voltage thresholds and feedback characteristics of the CMOS circuit. The logic memory cell uses the same physical transistor structures but operates them in three distinct stable states through carefully designed feedback loops and threshold voltages, achieving higher information density without requiring additional transistors or increasing power consumption from leakage current.
Data Source
AI summary
The present disclosure relates to a universal logic memory cell composed of triple-gate silicon devices. The universal logic memory cell according to one embodiment of the present disclosure may perform a ternary logic operation function and a memory function using triple-gate silicon devices driven by a positive feedback loop.