Triple-Gate Transistor Reverse Shallow Trench Isolation
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Solution Overview
Problem
Conventional multi-gate transistors face challenges such as high costs due to expensive silicon-on-insulator wafers, reduced carrier mobility from compressive stress in shallow trench isolation structures, and performance degradation as devices are scaled down, particularly due to insufficient gate wrap and short channel effects.
Innovation Solution
The method involves forming reverse shallow trench isolation (STI) structures by creating trenches through a dielectric layer on a semiconductor substrate, filling them with active area material, and isolating these areas with the remaining dielectric layers, which allows for improved vertical sidewalls and reduced isolation spacing, enabling more efficient device integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional shallow trench isolation structures are used, then isolation is provided, but compressive stress is generated in the channel region reducing carrier mobility and degrading device performance
Solution Approach 1:
The patent inverts the conventional STI approach by forming the isolation structure after defining the active area, rather than before. This reverse sequence allows the isolation structure to be formed without imposing compressive stress on the channel region, thereby maintaining carrier mobility while still providing effective isolation between devices
Solution Approach 2:
The patent performs preliminary actions by first defining the active area and forming the triple-gate structure before creating the isolation structure. This sequencing ensures that the channel region is already established and protected before the isolation material is deposited, preventing stress-induced mobility degradation
2Reliability
If SOI wafers are used for multi-gate transistors, then gate control over the channel is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent replaces expensive SOI wafers with standard silicon substrates, using a cost-effective alternative that achieves the same functional outcome. The isolation structure is formed using conventional materials and processes on readily available silicon substrates, eliminating the need for costly SOI processing while maintaining device performance
Solution Approach 2:
The patent changes the substrate parameter from SOI to standard silicon, and modifies the isolation structure parameters to achieve equivalent or superior performance. By adjusting the isolation formation sequence and structure geometry, the patent maintains gate control effectiveness while using cheaper substrates
3Productivity
If gate length is reduced to increase device density, then performance and power consumption are improved, but short channel effects increase causing DIBL and Vt roll-off
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional triple-gate control, wrapping the gate around three sides of the channel. This dimensional enhancement provides superior electrostatic control over the channel, effectively suppressing short channel effects even at reduced gate lengths and enabling higher device density
Data Source
AI summary
Example embodiments provide triple-gate semiconductor devices isolated by reverse shallow trench isolation (STI) structures and methods for their manufacture. In an example process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The example triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.