Triple-Gate Transistor Dual Stress Layers for Mobility
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Solution Overview
Problem
As transistor dimensions shrink, it becomes challenging to control short-channel effects and achieve high channel mobility and saturated drive currents, particularly in sub-0.1 micron devices, due to electrostatic charge sharing and fabrication difficulties in aligning gate electrodes in multiple-gate transistors.
Innovation Solution
The use of a first and second stress layer, such as silicon nitride, applied from opposite directions to the channel region in multiple gate transistors, effectively doubling charge carrier mobility and enabling accurate alignment of gate electrodes, thereby enhancing switching speed and drive currents in deep sub-micron transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor dimensions are scaled down to increase switching speed and drive currents, then device performance is improved, but short-channel effects increase and become difficult to control
Solution Approach 1:
The patent transitions from conventional planar single-gate transistors to triple-gate transistors, adding a vertical dimension to gate control. The third gate is positioned at the bottom of the channel region, beneath the substrate, enabling electrostatic control from three directions (top, sides, and bottom) rather than just one, thereby suppressing short-channel effects in scaled-down devices
Solution Approach 2:
The patent employs a composite structure with multiple gate electrodes (first gate at top, second gate on sides, third gate at bottom) and different material regions (channel region, source/drain regions, insulating regions) to achieve superior electrostatic control and resolve short-channel effects while maintaining high performance
2Reliability
If multiple-gate transistor structures are implemented to improve short-channel effects, then electrostatic control is enhanced, but fabrication alignment precision between gate electrodes becomes more difficult
Solution Approach 1:
The patent divides the gate structure into three separate gate electrodes positioned at different locations (top, sides, bottom) that can be fabricated and aligned independently. This segmentation allows each gate to be optimized and positioned separately, reducing the cumulative alignment errors that would occur in attempting to align multiple gates as a single integrated structure
Solution Approach 2:
The patent introduces insulating regions that serve as intermediaries between the gate electrodes and other structures. These insulating regions provide isolation and define precise spatial relationships, acting as reference structures that facilitate accurate alignment during fabrication processes
3Power
If channel doping is used in single gate transistors to improve performance, then drive currents are enhanced, but tunneling breakdown and dopant quantization problems occur
Solution Approach 1:
The patent replaces the conventional approach of using chemical doping (introducing impurity atoms) to enhance drive currents with an electrostatic control mechanism. The triple-gate structure creates strong electric field control over the channel, enabling high drive currents through field-effect modulation without requiring physical dopant atoms, thereby avoiding tunneling breakdown and dopant quantization effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases charge carrier mobility and switching speed, reduces short-channel effects, and enables the fabrication of high-performance transistors with ultrafine features, suitable for designs below 20 nm, while ensuring accurate gate alignment and high reliability.
Implementation Method 1
a first stress layer applying stress to the channel region from a first direction; and a second stress layer applying stress to the channel region from a direction opposite to the first direction
Data Source
AI summary
Multiple gate transistors are provided with a dual stress layer for increased channel mobility and enhanced effective and saturated drive currents. Embodiments include transistors comprising a first stress layer under the bottom gate and a second stress layer overlying the top gate. Embodiments further include transistors with the bottom gate within or through the first stress layer. Methodology includes sequentially depositing stressed silicon nitride, nitride, oxide, amorphous silicon, and oxide layers on a substrate having a bottom oxide layer thereon, patterning to define a channel length, depositing a top nitride layer, patterning stopping on the stressed silicon nitride layer, removing the amorphous silicon layer, epitaxially growing silicon through a window in the substrate to form source, drain, and channel regions, doping, removing the deposited nitride and oxide layers, growing gate oxides, depositing polysilicon to form gates, growing isolation oxides, and depositing the top stress layer.