Triple-Path CDR Oscillator for Jitter-Stable Clock Recovery
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Solution Overview
Problem
Clock and data recovery (CDR) circuits face challenges with large jitter due to process variations, temperature variations, and timing uncertainties in high-speed data transmission, which affect the stability and accuracy of clock recovery.
Innovation Solution
A triple-path structure CDR circuit with a sampling circuit, phase detector, processing circuits, and an oscillator circuit that generates an output clock based on detection results and digital codes, allowing for wide tuning range and high resolution, while achieving bandwidth tracking and loop stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional oscillator circuit is used in CDR, then the circuit structure is simple, but the jitter is large due to process variations, temperature variations, and timing uncertainties
Solution Approach 1:
The oscillator control is segmented into three independent paths: a proportional path for phase correction, an integral path for frequency correction, and a feedforward path for bandwidth tracking. Each path processes control signals separately and combines them at the oscillator input, allowing independent optimization of each function while maintaining overall system reliability and reducing jitter.
2Adaptability or versatility
If the oscillator tuning range is increased to cover frequency variations, then the frequency adaptation capability is improved, but the resolution of frequency control deteriorates
Solution Approach 1:
The single-dimensional frequency control is transformed into a three-dimensional control space with three independent paths: proportional control for phase alignment, integral control for cumulative frequency adjustment, and feedforward control for bandwidth tracking. This multi-dimensional approach allows the system to achieve both wide tuning range and high resolution by operating in multiple control dimensions simultaneously.
3Speed
If the loop bandwidth is increased to improve tracking speed, then the bandwidth tracking capability is improved, but the loop stability deteriorates
Solution Approach 1:
The loop bandwidth is made dynamic through the feedforward path that automatically adjusts the effective bandwidth based on the operating frequency. At different frequency corners, the feedforward gain varies to maintain optimal bandwidth, allowing the loop to track quickly at high frequencies while maintaining stability at low frequencies. This dynamic bandwidth adjustment resolves the contradiction between tracking speed and stability.
Data Source
AI summary
A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.