Triple-Path CDR Oscillator Tuning for Low Jitter Stability

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Solution Overview

Problem

Clock and data recovery (CDR) circuits face challenges with large jitter due to process variations, temperature variations, and timing uncertainties in high-speed data transmission, affecting oscillator circuit performance and loop stability.

Innovation Solution

A triple-path structure CDR circuit with a sampling circuit, phase detector, processing circuits, and an oscillator circuit that generates an output clock based on detection results and digital codes, allowing for wide tuning range and high resolution, while achieving bandwidth tracking and ensuring loop stability through coarse and fine tuning.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the oscillator circuit uses a large frequency step to widen the tuning range, then the tuning range is improved, but the jitter increases

Engineering Contradiction:

Improvetuning rangeVSAvoidjitter

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The frequency tuning process is segmented into two distinct paths: a first processing circuit that accumulates phase error information to generate a first digital code for fine frequency tuning, and a second processing circuit that accumulates a portion of the first digital code to generate a second digital code for coarse frequency tuning. This segmentation allows the system to achieve both wide tuning range and low jitter by combining fine adjustments (low jitter) with coarse adjustments (wide range).

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a dual-dimensional control structure by separating the frequency tuning into fine tuning (first digital code) and coarse tuning (second digital code) dimensions. The fine tuning path provides high precision with small frequency steps, while the coarse tuning path provides wide range with large frequency steps. This dimensional separation resolves the contradiction between tuning range and jitter.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Stability of the object's composition

If the CDR circuit uses a fixed loop bandwidth, then the loop stability is maintained, but the performance degrades at various frequency corners

Engineering Contradiction:

Improveloop stabilityVSAvoidbandwidth tracking

Core Design Contradiction:

Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic loop bandwidth adjustment by allowing the loop bandwidth to track the output clock frequency. The loop bandwidth is adjusted according to the frequency of the output clock signal, enabling the system to maintain optimal stability characteristics across different frequency corners. This dynamic adaptation resolves the contradiction between fixed stability and frequency-dependent performance.

Inventive Principle:

Principle #15Dynamics

3Reliability

If the oscillator circuit has high frequency resolution, then the jitter is reduced, but the tuning range is limited

Engineering Contradiction:

ImprovejitterVSAvoidtuning range

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The frequency control is segmented into fine tuning (high resolution, low jitter) and coarse tuning (wide range) components. The first processing circuit generates a first digital code with high resolution for fine frequency adjustment, while the second processing circuit generates a second digital code for coarse frequency adjustment. This segmentation enables the system to achieve both high frequency resolution and wide tuning range simultaneously.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges the fine tuning path and coarse tuning path in the oscillator circuit, combining the high-resolution first digital code with the wide-range second digital code. This merging allows the oscillator to achieve both high frequency resolution (from fine tuning) and wide tuning range (from coarse tuning), resolving the contradiction between these two parameters.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11569822B2Triple-path clock and data recovery circuit, oscillator circuit and method for clock and data recovery

Publication Date: 2023.01.31 M31 TECH

AI summary

A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.