Triple-Path PLL Circuit for Fast Lock and Stable Frequency Control
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Solution Overview
Problem
Existing PLL circuits face challenges in quickly locking phase due to the requirement for a slower response speed of oscillation frequency control by the third voltage signal to ensure stability, leading to delayed phase locking.
Innovation Solution
A PLL circuit with a triple path configuration, including a phase comparator, charge pumps, filters, a comparator, and a voltage-controlled oscillator, where the phase is quickly locked by prioritizing high-speed lock mode operations and subsequently performing low-response-speed offset frequency control, allowing for rapid phase locking without being restricted by moderate offset frequency control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the response speed of oscillation frequency control by the third voltage signal is set sufficiently slower to ensure stability of the PLL circuit, then the stability is improved, but the phase locking speed deteriorates
Solution Approach 1:
The patent divides the oscillation frequency control into two separate control paths: a first control path using the first voltage signal for rapid phase locking, and a second control path using the third voltage signal for stable offset frequency control. This segmentation allows each path to operate at different speeds without interfering with each other, resolving the contradiction between fast locking and stability.
Solution Approach 2:
The patent implements preliminary action by first performing rapid phase locking through the first control path before engaging the slower third voltage signal for offset frequency control. The phase is quickly locked initially, and then the offset control is applied subsequently, allowing the system to achieve both fast locking and stability.
2Measurement precision
If the third voltage signal is used for offset frequency control during initial phase locking, then the frequency accuracy is improved, but the phase locking time increases
Solution Approach 1:
The patent applies preliminary action by first achieving phase locking through the faster first control path before applying the offset frequency control via the third voltage signal. This sequence allows the system to lock phase quickly first, then refine the frequency accuracy subsequently, avoiding the time penalty of using slow offset control during initial locking.
Solution Approach 2:
The control process is segmented into two distinct phases: initial phase locking using the first voltage signal, and subsequent offset frequency adjustment using the third voltage signal. This temporal segmentation allows the system to prioritize speed during initial locking and accuracy during the refinement phase.
Data Source
AI summary
A PLL circuit includes a phase comparator, first and second charge pumps, a filter generating a first control voltage from a current of the first charge pump, a comparator comparing a voltage of a first node with a reference voltage, a switch section outputting the reference voltage to the first node and outputting a current of the second charge pump to a second node in a high-speed lock mode, and outputting the current of the second charge pump to the first node and outputting a result from the comparator to the second node in a normal lock mode, a second filter generating a second control voltage by integrating a current of the first node, a third filter generating a third control voltage by integrating a current of the second node, and a voltage controlled oscillator generating a clock signal of a frequency corresponding to the first to third control voltages.