Triple Patterning Lithography Color Conflict Reduction

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Solution Overview

Problem

Current photolithographic processes face limitations in printing small feature sizes and pitches due to physical constraints, leading to color conflicts in triple patterned integrated circuit designs, which hinder the fabrication of advanced ICs with dense layer layouts.

Innovation Solution

A method involving a design rule check (DRC) with restrictive design rules and conflict graph analysis is applied to determine the colorability of IC layouts, allowing for partial coloring and identification of non-colorable shapes, thereby reducing color conflicts in triple patterned designs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If photolithographic processes are used to print small feature sizes and pitches, then manufacturing precision is improved, but color conflicts occur in triple patterned designs

Engineering Contradiction:
Improvefeature size and pitch printing capabilityVSAvoidcolor conflict occurrence
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary actions by performing design rule checks and conflict graph analysis before the actual photolithographic printing process. The system identifies potential color conflicts in advance and adjusts the layout or coloring strategy to prevent conflicts from occurring during fabrication, thereby maintaining both manufacturing precision and reliability

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If triple patterning lithography is used to print dense layouts, then manufacturing precision is improved, but color conflicts increase

Engineering Contradiction:
Improvedense layout printing capabilityVSAvoidcolor conflict complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms through automated design rule checks and conflict graph analysis that evaluate the layout and coloring assignments. When potential color conflicts are detected, the system provides feedback to adjust the coloring strategy or layout configuration, enabling dense layout printing while managing color conflict complexity through iterative optimization

Inventive Principle:
Principle #23Feedback

3Device complexity

If traditional photolithographic processes are used, then device complexity is reduced, but manufacturing precision deteriorates for advanced ICs

Engineering Contradiction:
Improveprocess simplicityVSAvoidfeature size printing capability
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies segmentation by dividing the single photolithographic printing process into triple patterning lithography, which uses multiple exposure steps with different color assignments. This segmentation allows the system to achieve the manufacturing precision required for advanced ICs with smaller feature sizes and pitches, while the automated coloring algorithms help manage the increased process complexity

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9158885B1Reducing color conflicts in triple patterning lithography
Publication Date: 2015.10.13 GLOBALFOUNDRIES US INC
  • US9158885B1 patent drawing
  • US9158885B1 patent drawing
  • US9158885B1 patent drawing

AI summary

Methods of the present disclosure can include: using a computing device to perform actions including: applying a design rule check (DRC) on a proposed integrated circuit (IC) layout, wherein the DRC applies a set of restrictive design rules (RDRs) in response to the proposed IC layout being a contact area (CA) layout; computing a conflict graph for the proposed IC layout in response to one of the IC layout being a metal layer layout and the set of RDRs being satisfied; determining whether the IC layout is one of non-colorable, indeterminate, partially colorable, and fully colorable; and partially coloring the IC layout and identifying non-colorable nodes in response to the IC layout being indeterminate or partially colorable.