Triple-Patterning Friendly Placement via Cell Attribute Analysis
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Solution Overview
Problem
Conventional techniques for resolving triple-patterning (TP) design rule checking (DRC) violations in lithography are inefficient, leading to potential design errors and increased design time and cost due to placement abutment rules and post-placement fixes.
Innovation Solution
A design optimization methodology that generates triple-patterning-free standard cell layouts, identifies potential TP DRC violations through cell attribute generation, and inserts placement blockages to prevent violations, ensuring compliance with TP DRC rules during cell placement, thereby reducing design turn-around time and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If placement abutment rules are adopted to prevent TP DRC violations, then TP DRC compliance is improved, but placement flexibility and design area are worsened
Solution Approach 1:
The patent applies preliminary action by performing TP DRC violation detection and insertion of TP blockages during the placement phase, before finalization of the layout. This proactive approach identifies potential violations early and prevents them by restricting placement in specific regions, thereby maintaining TP DRC compliance without requiring complex post-placement corrections while preserving placement flexibility.
2Reliability
If post-placement-fixing techniques are implemented to resolve TP DRC violations, then TP DRC compliance is improved, but design time and turnaround are worsened
Solution Approach 1:
The patent performs TP DRC violation detection and inserts TP blockages during the placement phase itself, rather than as a post-placement fix. This preliminary action eliminates the need for time-consuming post-placement correction iterations, significantly reducing design turnaround time while ensuring TP DRC compliance is achieved from the outset.
Solution Approach 2:
The placement tool is enhanced with integrated TP DRC violation detection and blockage insertion capabilities, allowing the placement process to self-correct potential violations automatically during placement. This eliminates the need for separate post-processing steps and reduces overall design time while maintaining compliance.
3Productivity
If conventional placement methods are used without TP awareness, then placement speed is improved, but TP DRC violations are generated
Solution Approach 1:
The patent enhances the conventional placement tool with integrated TP DRC violation detection and automatic blockage insertion capabilities. This allows the placement process to maintain its speed while automatically identifying and preventing TP DRC violations during placement, eliminating the need for slower post-processing corrections and achieving both high productivity and TP DRC compliance.
Data Source
AI summary
The present disclosure is directed to a method for triple-patterning friendly placement. The method can include creating cell attributes identifying potential risk for triple-patterning design rule checking (TP DRC) violations in both a vertical and a horizontal propagation in a placement region. Based on these cell attributes, placement blockages can be inserted to prevent TP DRC violations after cell placement.