Triple-Transformer GaN Gate Drive for Low-Power CMTI Immunity
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Solution Overview
Problem
Existing transformer-based drive approaches for GaN power transistors face challenges in minimizing power consumption during the ON phase while maintaining low susceptibility to common mode transient immunity (CMTI) events.
Innovation Solution
A triple transformer configuration is introduced, where a first transformer drives the GaN enhancement mode power transistor, a second transformer uses a voltage clamping device to turn off the GaN depletion mode transistor, and a third transformer turns on the GaN depletion mode transistor, minimizing power dissipation during the ON phase and eliminating CMTI susceptibility by using a center-tapped coil for the turn OFF device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If two coreless transformers are used to drive a single GaN power transistor, then power consumption during the ON phase is reduced, but power is consumed during the OFF phase due to the biased resistor and the system becomes susceptible to CMTI events
Solution Approach 1:
The patent divides the drive function into three separate transformers, each dedicated to a specific function: turning on the power transistor, turning off the power transistor, and controlling the depletion mode transistor. This segmentation eliminates the need for a continuously biased resistor and prevents CMTI susceptibility by isolating control functions.
Solution Approach 2:
The patent introduces a depletion mode transistor as an intermediary device controlled by the third transformer to manage the turning off process. This intermediary mechanism provides precise control over the power transistor's off-state without requiring continuous power consumption or creating CMTI susceptibility.
2Reliability
If a normally ON failsafe device is used to drive the GaN power transistor, then the system is not susceptible to CMTI events, but power consumption during the ON phase increases significantly
Solution Approach 1:
The patent segments the control functions across three transformers, with the first transformer providing minimal power during the ON phase without requiring a Zener voltage to maintain failsafe operation. This segmentation eliminates the need for the normally ON failsafe device while maintaining reliability.
Solution Approach 2:
The depletion mode transistor serves itself by being naturally off without requiring continuous biasing, eliminating the need for power-consuming failsafe mechanisms while maintaining system reliability.
3Ease of operation
If a resistor is biased to turn off the GaN power transistor, then the transistor can be turned off, but power is continuously consumed during the OFF phase
Solution Approach 1:
The patent uses periodic action by employing the third transformer to periodically activate the depletion mode transistor only when needed for turning off the power transistor. This eliminates continuous power consumption associated with biased resistors while maintaining the ability to turn off the GaN power transistor on demand.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves low power consumption during both ON and OFF phases, with minimal power required during the ON phase and zero power consumption during the OFF phase, while maintaining robustness against CMTI events.
Implementation Method 1
a GaN enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer
Implementation Method 2
a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer
Implementation Method 3
a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer
Data Source
AI summary
A power stage includes: a first transformer; a second transformer; a third transformer; a GaN (gallium nitride) enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer; and a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer.