Triple Via Chain for Memory Interconnect Testing
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Solution Overview
Problem
Existing memory sub-systems face challenges in accurately detecting cracks, misalignments, and disconnections in advanced interconnects due to the limitations of single via chains, which can lead to incomplete testing of fabrication processes, especially in compact and high-density memory devices like 3D flash NAND memory.
Innovation Solution
Implementing a triple via chain system, where three independent via chains are used in each layer of the memory device, allowing for more comprehensive testing by transmitting signals across each chain to detect errors and stress points, thereby enhancing the accuracy of fabrication quality checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single via chain is used for testing, then the device complexity is reduced, but the measurement precision and reliability of interconnect testing deteriorates
Solution Approach 1:
The patent divides the testing system into three independent via chains instead of using a single via chain. Each via chain can independently test different aspects of the interconnect structure, allowing for more precise detection of cracks, misalignments, and disconnections while maintaining manageable device complexity through modular segmentation
2Ease of manufacture
If a single via chain is used for testing, then the manufacturing process is simpler, but the reliability of fabrication quality checks deteriorates
Solution Approach 1:
The manufacturing testing process is segmented into three independent via chain tests, each targeting specific interconnect layers or failure modes. This segmentation enables comprehensive quality verification without requiring overly complex manufacturing processes, as each via chain can be manufactured and tested independently
Solution Approach 2:
The via chains are incorporated into the fabrication process as preliminary test structures that enable quality checks before final device completion. This preliminary testing action allows for early detection of fabrication defects, improving overall quality reliability without adding significant manufacturing complexity
3Reliability
If three independent via chains are implemented, then the reliability and measurement precision of interconnect testing improves, but the device complexity increases
Solution Approach 1:
By segmenting the testing function into three specialized via chains, each chain can be optimized for specific testing purposes while maintaining independent operation. This segmentation improves reliability through comprehensive coverage of interconnect defects while managing complexity through functional specialization and independence
Solution Approach 2:
The three via chains collectively provide universal testing capability for various interconnect defects including cracks, misalignments, and disconnections. Each via chain serves multiple testing functions, allowing the system to achieve high reliability without proportionally increasing overall device complexity
Data Source
AI summary
A memory device can include a first portion having a memory array comprising a plurality of memory cells and a first via chain segment for performing a test operation. The memory device can include a second portion comprising processing circuitry and a second via chain segment for performing the test operation. The memory device can also include an interconnect coupling the first portion and the second portion, the interconnect comprising a third via chain segment, wherein the first via chain segment, second via chain segment, and third via chain segment can be selected independently.