Triple Well CMOS Latchup Robustness via Buried Layer Segmentation
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Solution Overview
Problem
Current triple well technology in MOSFET devices faces challenges with noise isolation and CMOS latchup, as the buried n+ layer must overlap n-wells to isolate the p-well, leading to spacing issues and modified critical parameters that affect latchup robustness.
Innovation Solution
The introduction of a buried n+ layer not only beneath the p-well but also beneath the n-well, along with additional isolation structures and a sub-collector region, to enhance latchup robustness and address spacing issues, while providing a p+ layer to compensate for n-channel MOSFET threshold voltage scattering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the buried n+ layer is placed below the p-well to isolate the p-well from the substrate, then noise isolation is improved, but latchup robustness deteriorates due to modified critical parameters
Solution Approach 1:
The invention divides the single buried n+ layer into two separate buried n+ layers: one positioned to isolate the p-well from the substrate (for noise isolation), and another positioned beneath the n-well (for latchup robustness). This segmentation allows each layer to independently fulfill its specific function without compromising the other, resolving the contradiction between noise isolation and latchup prevention.
Solution Approach 2:
The additional buried n+ layer acts as an intermediary element that provides low-impedance paths for charge dissipation, preventing latchup conditions while maintaining the isolation function of the original buried n+ layer. This intermediary structure enables simultaneous achievement of both noise isolation and latchup robustness.
2Object-affected harmful factors
If the buried n+ layer overlaps the n-wells to isolate the p-well, then isolation is improved, but spacing issues arise in the CMOS formation process
Solution Approach 1:
By segmenting the buried n+ layer structure into two separate layers with distinct horizontal positions, the invention eliminates the need for overlap between the buried n+ layer and n-wells. The first buried n+ layer is positioned to isolate the p-well without overlapping n-wells, while the second buried n+ layer is positioned beneath the n-well, thereby resolving spacing conflicts in the formation process.
3Reliability
If MOSFET threshold voltages are decreased to improve device performance, then device performance is improved, but noise isolation becomes more critical and latchup risk increases
Solution Approach 1:
The segmented buried n+ layer structure provides enhanced and differentiated isolation: the first layer isolates the p-well from the substrate to prevent substrate noise coupling, while the second layer provides low-impedance paths beneath the n-well to prevent latchup. This segmentation enables effective noise isolation and latchup prevention even at lower threshold voltages where these issues become more critical.
Solution Approach 2:
The invention creates a composite isolation structure using two buried n+ layers with different positioning and functional characteristics. This composite structure provides synergistic effects: one layer optimized for substrate isolation and another optimized for latchup prevention, enabling robust performance at lower threshold voltages where single-layer structures would be insufficient.
Data Source
AI summary
Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.