Triple-Well Avalanche Junction Layout for Low-Voltage ESD Protection

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Solution Overview

Problem

Conventional integrated circuit (IC) structures face challenges in reducing trigger voltage for electrostatic discharge (ESD) elements while maintaining or lowering the holding voltage, as ICs scale down, leading to increased sensitivity to electrostatic discharge events.

Innovation Solution

The integration of an avalanche junction within a doped semiconductor region over a semiconductor well, utilizing a triple well structure with specific doping types and insulative materials, allows for a bi-directional current pathway with a lower trigger voltage and reduced holding voltage, enabling effective electrostatic discharge protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If IC scale decreases, then device size reduces, but sensitivity to ESD events increases

Engineering Contradiction:

Improvedevice sizeVSAvoidESD sensitivity

Core Design Contradiction:

Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent changes key electrical parameters by introducing the avalanche junction with controlled doping concentrations and depths. The avalanche junction is positioned at a specific depth and has a controlled breakdown voltage that compensates for the reduced device size, maintaining appropriate ESD protection thresholds despite the smaller scale of the integrated circuit.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces the trigger voltage to at most approximately 9.5 volts while maintaining a holding voltage of at most approximately 5.0 volts, providing enhanced electrostatic discharge protection with minimal impact on device operation.

Implementation Method 1

an avalanche junction is defined between the collector region and the doped semiconductor region across the doped well

Methodology Applied

Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS12068308B2Integrated circuit structure with avalanche junction to doped semiconductor over semiconductor well

Publication Date: 2024.08.20 GLOBALFOUNDRIES US INC

AI summary

Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.