Triple-Well Semiconductor Device Latch-Up Immunity
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Solution Overview
Problem
The triple-well structure in semiconductor devices faces challenges in lowering resistance at the connection part of the shallow N well and deep N well, leading to potential latchup due to parasitic transistor generation during the manufacturing process.
Innovation Solution
The semiconductor device incorporates an element isolation structure where the element isolation films do not extend over the boundary between the first well and the second well, allowing for enhanced ion implantation to form wells and improve the connection between them, thereby reducing resistance and improving latch-up immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the element isolation film extends over the boundary between the shallow P well and the shallow N well, then the transistors are effectively isolated, but the resistance at the connection part of the shallow N well and deep N well increases and latchup occurs
Solution Approach 1:
The element isolation film is selectively positioned to cover only specific regions: it covers the shallow P well and extends to the boundary with the shallow N well, but deliberately does not cover the connection region between the shallow N well and deep N well. This local differentiation allows electrical connection between N wells while maintaining isolation where needed, resolving the contradiction between isolation effectiveness and connection quality.
2Reliability
If the element isolation film covers the entire boundary between P-type and N-type transistor formation areas, then transistor isolation is improved, but the connection between shallow N well and deep N well is disrupted
Solution Approach 1:
The element isolation film is segmented into distinct coverage regions rather than forming a continuous barrier. It is present in the P-type transistor formation area and extends to the boundary with the N-type area, but is intentionally absent from the connection region between shallow N well and deep N well. This segmentation enables simultaneous achievement of transistor isolation and well connection continuity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reinforces the connection between wells, lowers resistance, and enhances latch-up immunity by enlarging the connection part of the N wells, improving the overall performance of the triple-well structure.
Implementation Method 1
forming a first well by implanting ions into the region of the first well; forming a second well by implanting ions into the region of the second well; forming a third well by implanting ions under the first well
Data Source
AI summary
A semiconductor device includes: a first transistor and a second transistor disposed in or on a silicon substrate; an element isolation structure that isolates the first transistor and the second transistor, the element isolation structure comprising at least one of a first element isolation film disposed in a region of a first well disposed in a formation area of the first transistor, or a second element isolation film disposed in a region of a second well disposed in a formation area of the second transistor, and a third well disposed under the first well in the silicon substrate and is electrically connected to the second well. The first element isolation film or the second element isolation film has a portion that does not extend over a boundary between the first well and the second well.