Triple Well Semiconductor Latch-Up Suppression via Fourth Well
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Solution Overview
Problem
Semiconductor devices with a triple well structure often experience a latch-up phenomenon due to parasitic thyristors, which can lead to damage from excessive current flow and heat generation, and existing methods to prevent this either reduce junction withstand voltage or risk dielectric breakdown.
Innovation Solution
A semiconductor device with a triple well structure is designed by forming a fourth well with a lower impurity concentration than the third well, adjacent to the third N-well, to increase junction withstand voltage and suppress latch-up by maintaining a reverse-biased PN junction, allowing for a lower reference potential without avalanche breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a triple well structure is used to suppress latch-up, then reliability is improved, but parasitic thyristors are formed which can cause latch-up under certain conditions
Solution Approach 1:
The patent extracts and eliminates the parasitic thyristor structure by removing the continuous P-type substrate connection. Instead of using a traditional P-type substrate, the invention introduces an N-type isolation layer between the P-type substrate and the P-well regions, effectively taking out the harmful parasitic path while maintaining the beneficial triple well structure for latch-up suppression.
Solution Approach 2:
The patent introduces an N-type isolation layer as an intermediary between the P-type substrate and the P-well regions. This intermediary layer blocks the formation of parasitic thyristors by preventing the continuous P-type region needed for thyristor operation, while still allowing the triple well structure to function for suppressing latch-up phenomena.
2Reliability
If reference potential is lowered to suppress latch-up, then reliability is improved, but junction withstand voltage is reduced risking dielectric breakdown
Solution Approach 1:
The patent extracts the problematic voltage suppression mechanism (lowering reference potential) and replaces it with a structural solution. By removing the continuous P-type substrate connection through the N-type isolation layer, the invention eliminates parasitic thyristors without needing to lower the reference potential, thereby maintaining high junction withstand voltage and avoiding dielectric breakdown risks.
Solution Approach 2:
The N-type isolation layer acts as an intermediary that provides electrical isolation between the P-type substrate and P-well regions. This intermediary structure suppresses latch-up by blocking parasitic current paths while maintaining the original reference potential level, thus preserving the junction withstand voltage and preventing dielectric breakdown.
3Strength
If fourth well with lower impurity concentration is formed adjacent to third N-well, then junction withstand voltage is increased, but device complexity increases
Solution Approach 1:
The patent merges the function of the fourth well with the N-type isolation layer. Instead of creating a separate fourth well structure, the invention combines the isolation function with the voltage enhancement function into the existing N-type isolation layer, thereby increasing junction withstand voltage without adding significant structural complexity.
Solution Approach 2:
The N-type isolation layer is given multiple functions: it provides electrical isolation to eliminate parasitic thyristors, enhances junction withstand voltage by creating a reverse-biased junction with P-well regions, and maintains proper biasing conditions. This multi-functionality avoids the need for additional separate structures like a fourth well.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses the latch-up phenomenon by increasing junction withstand voltage and allowing for a lower reference potential, preventing current flow that would otherwise lead to device damage, while maintaining element behavior and electrical isolation.
Implementation Method 1
forming a fourth well (20), of the same conductivity type as the semiconductor substrate, in a surface region of the main surface of the semiconductor substrate contacting the third N-well (18) without the first N-well (14) being formed, at a lower concentration than the third N-well (18)
Data Source
AI summary
In a semiconductor substrate having a first well of a conductivity type opposite to that of the semiconductor substrate, formed on part of a main surface of the semiconductor substrate, a second well of the same conductivity type as the semiconductor substrate, formed on part of a surface region of the first well shallower than the first well, and a third well of a conductivity type opposite to that of the semiconductor substrate, formed in a surface region of the first well, in a region where the second well is not formed and shallower than the first well, by having a fourth well, formed in a region of the main surface of the semiconductor substrate where the first well is not formed and doped with impurities of the same conductivity type as the semiconductor substrate at a lower concentration than the third well, and controlling a reference voltage to be low, it is possible suppress the occurrence of a latch up phenomenon.