Triple Well Memory Cell for Single Event Upset Tolerance
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Solution Overview
Problem
Current CMOS memory cells are insufficiently tolerant to high-energy particle hits, as the separation of redundant nodes may not provide sufficient Single Event Upset (SEU) tolerance, especially in smaller technology designs where the charge required to upset data values decreases, and higher energy ions can still affect the memory cell.
Innovation Solution
The implementation of a memory cell design using multiple well techniques, where transistors are fabricated in isolated wells with well taps to confine charge generated by ion hits, preventing it from affecting other nodes, and using cross-coupled inverters with PMOS and NMOS transistors in series or parallel configurations to restore data values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard CMOS fabrication is used, then manufacturing simplicity is maintained, but SEU tolerance is insufficient
Solution Approach 1:
The patent divides the semiconductor structure into multiple isolated wells (first well, second well, third well, fourth well) that are electrically isolated from each other. Each well contains specific transistors and can independently dissipate charge, preventing charge accumulation that would cause SEU. This segmentation allows standard CMOS fabrication while achieving SEU tolerance through structural division.
2Productivity
If technology design size is reduced, then device integration is improved, but charge required to upset data values decreases making SEU tolerance worse
Solution Approach 1:
By segmenting the transistor structure into multiple isolated wells, the patent ensures that even in small technology designs, charge generated by ion hits is confined to individual wells and dissipated independently. This prevents charge from affecting other nodes, maintaining SEU tolerance despite reduced device dimensions and higher integration density.
Solution Approach 2:
The isolated wells act as intermediaries that capture and contain charge generated by ion hits. Each well serves as a separate charge dissipation path, preventing charge from propagating to other parts of the circuit. This intermediary structure maintains SEU tolerance in scaled-down designs where charge effects are more pronounced.
3Reliability
If redundant nodes are separated, then some SEU protection is achieved, but higher energy ions can still affect the memory cell
Solution Approach 1:
The patent extends segmentation to the well level, creating four electrically isolated wells that completely surround and isolate each transistor. This deep segmentation prevents charge from higher energy ion hits from affecting multiple nodes, as each well independently dissipates charge through its dedicated tap, providing enhanced protection against high-energy particles.
Solution Approach 2:
Each well is given unique local properties through electrical isolation and dedicated charge dissipation paths. The first and second wells are isolated from the third and fourth wells, creating localized charge management zones. This local quality ensures that ion hits affecting one area do not propagate to other areas, enhancing protection against high-energy particles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances SEU tolerance by isolating charge within individual wells, effectively preventing data upsets even in smaller technology designs, ensuring reliable operation under high-energy ion impacts.
Implementation Method 1
The first well, second well, third well, and fourth well are isolated from each other
Data Source
AI summary
A memory cell (300) having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first transistor (306) of a first type is in a first well (334) of a second type having a first well tap (342). A second transistor (308) of the first type is in a second well (336) of the second type having a second well tap (344). A third transistor (310) of the second type is in a third well (338) of the first type having a third well tap (346); and a fourth transistor (312) of the second type is in a fourth well (340) of the first type having a fourth well tap (348). The first well, second well, third well, and forth well are isolated from each of the other wells.