Triple-Well IC Noise Isolation for High-Speed Serial Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed serial transfer interfaces in integrated circuit devices, such as those used in portable telephones, face challenges with noise interference due to small voltage amplitudes, affecting both the high-speed interface circuit and the driver circuit, leading to reduced transmission quality.
Innovation Solution
The integration of a triple-well structure and substrate potential stabilization diffusion regions in the integrated circuit device, where transistors in the high-speed interface circuit block are formed in specific conductivity-type wells, and the driver logic circuit block is separated from the high-speed interface circuit block, reducing noise transmission and improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If high-speed interface circuit and driver logic circuit are integrated in the same substrate, then device complexity is reduced and layout efficiency is improved, but noise interference between circuits increases affecting transmission quality
Solution Approach 1:
The substrate is divided into multiple isolation regions with different conductivity types. The high-speed interface circuit is placed in a first isolation region while the driver logic circuit is placed in a second isolation region. These regions are electrically isolated through opposite conductivity type wells, allowing both circuits to coexist on the same substrate without mutual noise interference.
Solution Approach 2:
Wells with opposite conductivity types serve as intermediary structures between the high-speed interface circuit and driver logic circuit. These wells act as electrical barriers that block noise transmission while allowing both circuits to function on the same substrate, thus mediating the conflict between integration and noise isolation.
2Object-affected harmful factors
If small voltage amplitude differential signals are used for high-speed serial transfer, then EMI noise is reduced and power consumption is lowered, but the circuit becomes more sensitive to internal noise affecting transmission quality
Solution Approach 1:
The substrate is segmented into isolated conductivity regions that physically and electrically separate noise-sensitive high-speed interface circuits from noise-generating driver logic circuits. This segmentation allows small voltage amplitude differential signals to be used for low EMI and power consumption while protecting transmission quality through electrical isolation.
3Ease of manufacture
If transistors of different conductivity types are formed in the same well region, then manufacturing process is simplified, but noise transmission between circuits increases
Solution Approach 1:
Instead of forming all transistors in a single well region, the substrate is segmented into multiple well regions with alternating conductivity types. Each circuit block is confined to wells of its required conductivity type, preventing noise transmission while maintaining manufacturing feasibility through standard CMOS multi-well processes.
Solution Approach 2:
Different regions of the substrate are assigned different conductivity types according to the specific requirements of each circuit block. The high-speed interface circuit uses wells of one conductivity type while the driver logic circuit uses wells of the opposite conductivity type, optimizing each region's electrical characteristics and noise performance.
Data Source
AI summary
An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included in the high-speed I/F circuit block is formed in a first-conductivity-type well formed in a second-conductivity-type substrate to enclose the second-conductivity-type well. A first-conductivity-type transistor and a second-conductivity-type transistor included in the driver logic circuit block are formed in a region other than a region of the first-conductivity-type well for the high-speed interface circuit block.