Triple-Well Capacitor Structure for Lower RF Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
RFICs for wireless mobile communications face challenges in impedance matching, low noise characteristics, and the need for wide bandwidth and high output power, particularly in ultra wideband RADAR applications, with issues in parasitic capacitance affecting performance.
Innovation Solution
A capacitor structure with a triple well configuration and choke impedance elements, and a switch structure with stacked transistors and choke impedance elements, are designed to reduce parasitic capacitance and improve reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitor structures are used in RFICs, then the basic capacitance function is achieved, but parasitic capacitance increases which degrades performance
Solution Approach 1:
The capacitor structure is segmented into multiple conductivity type regions (first conductivity type, second conductivity type, and third conductivity type) within the semiconductor substrate. This segmentation creates isolated regions that reduce parasitic capacitance between adjacent capacitor elements while maintaining the required capacitance function.
Solution Approach 2:
Different regions of the semiconductor substrate are assigned different conductivity types to create local electrical properties that minimize parasitic effects. The first, second, and third conductivity type regions are strategically positioned to reduce unwanted capacitance coupling while preserving the capacitor's primary function.
2Ease of manufacture
If chip size is reduced to lower package price, then cost is reduced, but parasitic capacitance effects become more significant
Solution Approach 1:
The conductor pattern is designed with nested or interdigitated structures where conductive regions are arranged in a space-efficient manner. This nesting allows multiple capacitor elements to be packed into a smaller area while the conductivity type regions maintain electrical isolation to reduce parasitic capacitance.
Solution Approach 2:
The patent utilizes vertical dimensionality by creating multiple conductivity type regions at different depths or positions within the semiconductor substrate. This three-dimensional arrangement allows compact planar footprint while maintaining electrical isolation through the substrate depth, reducing parasitic capacitance in a smaller chip area.
Data Source
AI summary
A capacitor structure includes a semiconductor substrate, a first well, a second well, a first electrode, a second electrode, a first choke impedance element and a second choke impedance element. The semiconductor substrate includes an outer well having a first conductivity type. The first well is disposed in the outer well and has a second conductivity type. The second well is disposed in the first well and has the first conductivity type. At least portions of the first and second electrodes contact the second well. The first choke impedance element is connected between the second well and a ground voltage. The second choke impedance element is connected between the first well and a power supply voltage.