Triple Wiring Link Structure to Prevent Display Panel Pol-Melting
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Solution Overview
Problem
Conventional display devices experience a pol-melting phenomenon due to heat generation caused by increased current density in densely integrated signal wirings, leading to issues with high luminance, power consumption, and bezel size.
Innovation Solution
A display device incorporating a triple wiring structure with low-resistance metal in link portions to reduce current density, comprising a substrate with active and non-active areas, circuit films, metal layers, buffer layers, gate insulating films, signal wirings, and low-temperature passivation layers, where the link and signal wirings are electrically connected through contact holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a plurality of signal wirings are integrated in a limited space, then wiring density increases and device complexity is reduced, but current density increases causing heat generation and pol-melting phenomenon
Solution Approach 1:
The patent applies different material properties to different parts of the wiring structure. Specifically, it uses a low-resistance metal layer (such as aluminum or copper) in the link portion where multiple signal wirings are integrated, while other portions may use different materials. This local differentiation of material quality allows the integrated wiring region to handle higher current density without excessive heat generation, thus resolving the contradiction between wiring integration and heat generation.
Solution Approach 2:
The patent changes the electrical resistance parameter of the metal layer in the link portion by selecting low-resistance materials. This parameter change enables the wiring structure to accommodate higher current density in the integrated region without generating excessive heat, thereby allowing greater wiring integration while controlling heat generation and preventing the pol-melting phenomenon.
2Illumination intensity
If current density is increased to improve luminance, then display brightness improves, but heat generation increases causing pol-melting
Solution Approach 1:
The patent implements local quality differentiation by using a low-resistance metal layer specifically in the link portion where signal wirings are integrated. This localized material optimization allows the wiring to carry higher current density required for improved luminance while minimizing heat generation through the reduced resistance, thus enabling high brightness without causing pol-melting.
Solution Approach 2:
The patent changes the resistance parameter of the metal layer in the critical link portion to a lower value. This parameter change allows the system to achieve the higher current density needed for improved luminance while controlling the heat generation (since P=I²R), thereby resolving the contradiction between luminance improvement and heat generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents pol-melting, enables high luminance, reduces power consumption, and allows for a narrower bezel by minimizing heat generation and optimizing wiring area.
Implementation Method 1
a first link portion connected to a connection wiring of the circuit film in the non-active area, the first link portion including: a first metal layer disposed on the substrate
Implementation Method 2
the first link wiring and the first signal wiring and the first signal wiring and the first metal layer are electrically connected through contact holes, respectively
Data Source
AI summary
A display device capable of preventing a pol-melting phenomenon of a display panel, by reducing heat generation of the display panel by lowering current density, through including a triple wiring structure including a low-resistance metal in a link portion where a plurality of signal wirings are integrated.


