Tripwire Data Merging Circuit for Multi-Processor Debug Area Reduction
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Solution Overview
Problem
Current processor architectures require substantial integrated circuit area for instruction counters and associated control circuitry, limiting the miniaturization of processors, and there is a need for efficient mechanisms to communicate debug information from multiple processors to a debug station.
Innovation Solution
The picoengine processor, which lacks an instruction counter and associated circuitry, executes a tripwire instruction to output unique multi-bit values onto a tripwire bus, and a Tripwire Data Merging and Collision Detection Circuit (TDMCDC) consolidates these values onto a common bus for external debugging, enabling efficient communication of debug data from a pool of processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional processor architectures with instruction counters and control circuitry are used, then debugging and monitoring capabilities are provided, but integrated circuit area increases significantly
Solution Approach 1:
The patent extracts the debugging and monitoring function from the traditional processor core by implementing a separate tripwire instruction execution mechanism. This allows the processor to maintain minimal core functionality while providing debug capabilities through dedicated tripwire instructions that can be executed and monitored independently, thus reducing the area required for traditional instruction counters and control circuitry.
Solution Approach 2:
The tripwire bus acts as an intermediary between multiple picoengine processors and the external debug station. Instead of each processor requiring its own extensive control circuitry for debugging, the tripwire bus provides a shared communication medium that enables monitoring and debugging functionality across the entire pool of processors, thereby reducing individual processor area requirements.
2Productivity
If multiple processors output debug information simultaneously onto a shared bus, then communication efficiency to external debug station is improved, but signal collisions occur between processors
Solution Approach 1:
The tripwire bus implementation includes feedback mechanisms where processors monitor the bus state before outputting debug information. This feedback approach allows processors to detect when the bus is currently being used by another processor and defer their output accordingly, preventing signal collisions while maintaining efficient use of the shared communication medium.
Solution Approach 2:
The system employs periodic arbitration and controlled access to the tripwire bus, where processors take turns outputting debug information in a structured sequence. This periodic action pattern ensures that multiple processors can communicate debug data efficiently over time without simultaneous conflicts, as each processor is granted access to the bus during its designated time slot.
Data Source
AI summary
An integrated circuit includes a pool of processors and a Tripwire Data Merging and Collision Detection Circuit (TDMCDC). Each processor has a special tripwire bus port. Execution of a novel tripwire instruction causes the processor to output a tripwire value onto its tripwire bus port. Each respective tripwire bus port is coupled to a corresponding respective one of a plurality of tripwire bus inputs of the TDMCDC. The TDMCDC receives tripwire values from the processors and communicates them onto a consolidated tripwire bus. From the consolidated bus the values are communicated out of the integrated circuit and to a debug station. If more than one processor outputs a valid tripwire value at a given time, then the TDMCDC asserts a collision bit signal that is communicated along with the tripwire value. Receiving tripwire values onto the debug station facilitates use of the debug station in monitoring and debugging processor code.