Tristate Buffer Clock Gating With Delayed Glitch Protection
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Solution Overview
Problem
Tristate buffers in electronic devices often experience glitches when switched into a high impedance state, particularly in asynchronous systems, which can lead to malfunctions due to coincidental switching with clock signal edges.
Innovation Solution
A tristate buffer circuit with a regenerative loop and input delay stage that uses a gating stage to ensure the buffer switches into high impedance only when there are no signal transitions, preventing glitches by maintaining the output signal level and delaying the switching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the tristate buffer is switched asynchronously into high impedance state, then the buffer can be switched at any time within a clock period, but glitches may occur when switching coincides with clock signal edges
Solution Approach 1:
The gating stage checks the input signal and delayed signal before enabling the tristate buffer to switch into high impedance state. This preliminary check ensures that switching only occurs when no signal transition is propagating through the delay stage, preventing glitches while maintaining asynchronous switching capability
Solution Approach 2:
The gating stage acts as an intermediary between the tristate signal and the tristate buffer control input. It mediates the switching action by conditionally enabling the high impedance state only when safe, thus resolving the contradiction between flexible asynchronous switching and glitch-free operation
2Reliability
If the tristate buffer switches synchronously with clock edges, then glitches are avoided, but the clock can only be switched at appropriate moments with safety margin
Solution Approach 1:
The delay stage creates a time window before the clock edge by delaying the input signal. The gating stage uses this delayed signal to determine whether switching is safe, enabling asynchronous control while maintaining reliability by preventing switches during critical periods
Solution Approach 2:
The circuit uses its own delayed output signal to control the switching timing. The tristate buffer's output is fed back through the delay stage to the gating stage, which automatically prevents switching during signal transitions without external synchronization
Data Source
AI summary
A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an input signal to the tristate buffer and a gating stage having inputs for the input signal, a delayed input signal and an asynchronous tristate control signal and an output supplying the configuration signal to the tristate buffer. The gating stage sets the configuration signal to the high impedance mode only when the tristate control signal is set and the input signal and the delayed input signal have logic levels indicating that no signal transition of the input signal propagates within the delay stage. Depending upon signal polarity, the input signal and the delayed input signal are required to have the same digital state or opposite digital states.