Tristate Multiplexer Circuit to Prevent Idle Transistor Aging
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Solution Overview
Problem
Modern integrated circuits, particularly programmable logic devices, suffer from aging effects such as bias temperature instability (BTI) and hot carrier injection (HCI), which cause transistor degradation and performance reduction, especially in unused or biased portions of the circuitry, leading to issues like clock skew when aged and unaged logic circuits are used together.
Innovation Solution
A multiplexing circuit with an input selection stage and a tristate buffer stage, including aging prevention circuitry that nullifies gate-to-source voltage on output driving transistors by using tie-off transistors to set their gate voltage to zero volts during the tristate mode, effectively eliminating stress and preventing aging effects when the circuit is not actively used.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage stress is reduced to mitigate aging effects, then transistor degradation is slowed, but circuit performance is reduced
Solution Approach 1:
The circuit dynamically switches between two operational modes: active mode where transistors operate with full voltage stress for optimal performance, and tristate mode where tie-off transistors are activated to nullify gate-to-source voltage and eliminate aging effects. This dynamic adaptation allows the circuit to optimize between performance and reliability based on operational requirements
Solution Approach 2:
The tie-off transistors are pre-positioned in parallel with the output driving transistors, ready to be activated when the multiplexer enters tristate mode. This preliminary arrangement allows immediate protection against aging effects when the circuit transitions to idle state, preventing degradation before it occurs
2Stability of the object's composition
If programmable logic is left in a biased state for extended periods, then configuration stability is maintained, but aging effects cause threshold voltage changes and clock skew
Solution Approach 1:
The circuit periodically transitions unused programmable logic from a biased state to a tristate mode with nullified voltage stress. This periodic activation of tie-off transistors during idle periods prevents cumulative aging effects while maintaining configuration stability, eliminating the source of threshold voltage drift and clock skew
3Reliability
If tie-off transistors are added to nullify gate-to-source voltage, then aging effects are prevented, but device complexity increases
Solution Approach 1:
The tie-off transistors are merged with the existing output driving transistors in a parallel configuration within the same multiplexer structure. This integration allows the aging prevention function to be added without requiring separate dedicated circuits, minimizing the increase in device complexity while achieving reliable aging protection
Data Source
AI summary
An integrated circuit with programmable logic is provided. The programmable logic may include multiplexers that are actively used by a custom logic design or unused. To ensure that these multiplexers do not suffer from aging effects when they are not in use, the multiplexers may be provided with aging prevention circuitry. In particular, such a multiplexer may include an input selection stage that is coupled in series with a tristate buffer stage. The input selection stage may include pass transistors or full CMOS transmission gates. The tristate buffer stage may include at least two pairs of output driving transistors, with gates that are selectively shorted when the multiplexer is activated using additional transmission gate circuits. The aging prevention circuitry may include tie-off transistors that are activated to drive the gate-to-source voltages of the output driving transistors to zero volts whenever the multiplexer is not in use.