Tri-Gate Array Substrate Asymmetric Subpixel Arrangement
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Solution Overview
Problem
Conventional tri-gate driver structures in liquid crystal displays (LCDs) suffer from poor pixel charging ability, leading to inadequate charging and substandard display quality, including incomplete charging and color shift issues.
Innovation Solution
An array substrate with a tri-gate structure is designed, where six consecutive display pixels are arranged in a pixel unit with varying subpixel orders (RGB, RBG, GRB, BRG, BGR) to compensate for brightness, ensuring each subpixel is adequately charged and mixed to improve color mixture and display effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional tri-gate driver structure is used, then the data line width is reduced to one-third, but the pixel charging ability becomes poor resulting in inadequate charging and substandard display quality
Solution Approach 1:
The patent applies asymmetry by arranging subpixels in non-uniform patterns (RGB, RBG, GRB, GBR, BRG, BGR) across different pixel units rather than using a uniform arrangement. This asymmetric distribution optimizes the charging paths and electric field distribution for the tri-gate driver structure, improving pixel charging ability while maintaining the reduced data line width benefit
Solution Approach 2:
The patent implements local quality by making each pixel unit have a unique subpixel arrangement pattern selected from six different permutations. This localized variation in subpixel configuration optimizes the charging characteristics for each specific region, ensuring adequate charging ability across the entire display while maintaining the compact tri-gate structure
2Area of stationary object
If the tri-gate driver structure is used, then the data chip on film size is reduced to one-third, but the display quality becomes substandard due to poor pixel charging
Solution Approach 1:
The asymmetric subpixel arrangement patterns compensate for the reduced data chip size by optimizing the electric field distribution and charging paths within the compact tri-gate structure, ensuring adequate charging performance despite the smaller area
Solution Approach 2:
By varying the subpixel arrangement in each pixel unit, the patent optimizes the local charging characteristics to maintain high display quality even with the reduced data chip on film size imposed by the tri-gate driver structure
3Loss of time
If the tri-gate driver structure is used, then the gate pulse width and charging time are reduced to one-third, but the pixel charging ability becomes insufficient leading to bad image display
Solution Approach 1:
The asymmetric subpixel arrangements (RGB, RBG, GRB, GBR, BRG, BGR) are specifically designed to optimize charging within the reduced one-third gate pulse width, creating efficient charging paths that compensate for the shorter charging time
Solution Approach 2:
The localized variation in subpixel patterns optimizes the charging efficiency for each pixel unit, ensuring that adequate charging is achieved within the reduced time frame imposed by the tri-gate driver structure's faster gate pulse width
Data Source
AI summary
An array substrate includes a plurality of display pixels arranged in an array. Each of the plurality of display pixels comprises a red subpixel R, a green subpixel G, and a blue subpixel B. Six of the consecutive display pixels arranged horizontally and/or longitudinally as a whole are repeatedly arranged in a pixel unit. An arrangement order of the subpixels in each of the six consecutive display pixels is totally different. The subpixels in the six consecutive display pixels are arranged as RGB, RBG, GRB, GBR, BRG, and BGR successively. The technical problems of the conventional tri-gate driver structure, such as poor image display and display quality, are resolved due to poor charging ability of pixels which are inclined to incomplete charging.