TRNG Entropy Evaluation for Higher-Order Repetition Detection

The patent segments the entropy evaluation into multiple independent test components (repetition count test, adaptive proportion test, block repetition test) that can be executed separately. Each test focuses on specific aspects of entropy detection, allowing the system to achieve comprehensive measurement precision without requiring a single complex test mechanism.

The patent evaluates higher-order derivatives of the bitstream by examining patterns across multiple bit positions and time intervals. Instead of analyzing only immediate consecutive bits, the system looks at bit patterns separated by specific distances and evaluates derivatives of increasing order, adding dimensional depth to the entropy detection without proportionally increasing hardware complexity.

The entropy evaluator is designed to be self-sufficient, using only the random bitstream output from the TRNG as its input. The system performs all entropy evaluation computations internally using simple logical operations and counters, without requiring external complex hardware assistance. This self-service approach minimizes energy consumption while maintaining measurement precision.

The patent replaces complex mechanical or hardware-based entropy testing mechanisms with software-based or logic-based evaluation algorithms. By using digital logical operations, counters, and pattern recognition algorithms instead of complex physical testing hardware, the system achieves high measurement precision with significantly reduced energy consumption.

The patent designs counters and evaluation logic that serve multiple functions. The same counter infrastructure is reused across different test types (repetition count, adaptive proportion, block repetition) and different derivative orders. A single counter can evaluate multiple bit patterns by adjusting the evaluation logic, eliminating the need for separate dedicated counters for each test scenario.

The system achieves higher-order derivative evaluation by changing evaluation parameters (such as the distance between compared bit positions and the order of derivatives) rather than adding physical hardware components. The same hardware counters can evaluate different derivative orders by modifying the logical comparison parameters, maintaining measurement precision while minimizing device complexity.