Automated Test Generation for Trojan Detection
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Solution Overview
Problem
Existing delay-based side-channel analysis techniques are ineffective in detecting hardware Trojans due to negligible delay differences between golden and Trojan-inserted designs, and they struggle with generating robust delay signatures, especially in the presence of process variations and environmental noise.
Innovation Solution
An automated test generation algorithm is developed to produce test patterns that activate trigger conditions and change critical paths, maximizing path delay differences between golden and Trojan-inserted designs, using a combination of Boolean satisfiability-based and Hamming-distance reordering techniques to enhance side-channel sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing delay-based side-channel analysis techniques are used, then the detection process is simple, but the delay difference between golden design and Trojan inserted design is negligible making detection ineffective
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing delay signatures for all possible test patterns in a lookup table before actual Trojan detection. This pre-computation enables the system to quickly compare actual delay measurements against expected values, significantly improving detection effectiveness without adding complexity to the real-time measurement process.
Solution Approach 2:
The patent changes the measurement parameter from simple path delay to delay signature which captures the temporal characteristics of signal transitions. By analyzing the timing patterns of multiple signal transitions rather than single delay values, the system achieves higher measurement precision that can distinguish Trojan-induced delays from normal circuit variations.
2Ease of manufacture
If random or ATPG based test patterns are used, then test generation is straightforward, but robust delay signature creation is not effective
Solution Approach 1:
The patent pre-computes delay signatures for all possible input test patterns and stores them in a lookup table during the design phase. This preliminary action ensures that robust delay signatures are available before actual testing, eliminating the need for complex real-time signature generation while maintaining high measurement precision for Trojan detection.
Solution Approach 2:
The patent creates copies of delay signature data in a lookup table structure, allowing rapid retrieval and comparison during testing. Instead of regenerating delay signatures during each test operation, the system copies pre-computed signature data for comparison, significantly improving both ease of manufacture and measurement precision.
3Device complexity
If traditional Trojan detection methods are used, then the design process is simple, but detection accuracy is low especially in large designs with process variations and noise
Solution Approach 1:
The patent performs preliminary computation of delay signatures and creates lookup tables during the design phase, before actual Trojan detection occurs. This pre-computation approach captures the intended circuit behavior under various conditions, enabling accurate comparison during testing even in the presence of process variations and noise, thereby improving detection accuracy without proportionally increasing system complexity.
Solution Approach 2:
The patent replaces complex real-time delay signature computation with a simplified lookup table comparison mechanism. By substituting the mechanical computation process with a data retrieval and comparison operation, the system achieves high detection accuracy while keeping the actual detection system relatively simple.
Data Source
AI summary
The present disclosure describes various embodiments of systems, apparatuses, and methods for detecting a Trojan inserted integrated circuit design using delay-based side channel analysis. In one such embodiment, an automated test generation algorithm produces test patterns that are likely to activate trigger conditions and change critical paths of an integrated circuit design.