3D Trough ESD Protection Circuit Area Reduction
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Solution Overview
Problem
Conventional ESD protection circuits in semiconductor devices occupy excessive area due to the size of PMOS/NMOS components and diodes, making them vulnerable to electrostatic discharge threats as semiconductor manufacturing processes become more compact.
Innovation Solution
A 3D semiconductor device structure is implemented using trough structures with higher doping concentration layers and insulation layers, forming resistors and capacitors that reduce the area occupied by ESD protection circuits by arranging components perpendicular to the substrate surface, thereby utilizing the substrate efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits using PMOS/NMOS or diodes are used, then ESD protection function is achieved, but the circuit occupies excessive area
Solution Approach 1:
The patent transitions from planar 2D circuit layout to 3D vertical structure by forming trough structures that extend into the substrate. The ESD protection circuit components (resistors, capacitors, diodes) are arranged in three dimensions using depth方向的 trough structures, allowing vertical stacking and significantly reducing the horizontal footprint of the circuit while maintaining full ESD protection functionality
Solution Approach 2:
The patent implements nesting by placing multiple functional layers within the trough structures. The substrate contains embedded trough structures that hold doping layers, insulation layers, and conductive layers in a nested configuration. The first and second trough structures are nested within the substrate, with each trough containing multiple functional layers stacked vertically, achieving compact integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D structure significantly reduces the area occupied by ESD protection circuits, enhancing protection against electrostatic discharges while minimizing substrate usage, effectively addressing the vulnerability of compact semiconductor devices.
Implementation Method 1
The separation part of the substrate forms a resistor, which is coupled between the first contact and the second contact
Implementation Method 2
the second doping layer, the second insulation layer and the second conductive layer together form a capacitor, which is coupled between the second contact and the third contact
Data Source
AI summary
A method of manufacturing a semiconductor device, comprising: providing a substrate; forming a first trough structure, which comprises at least a first sidewall, on the substrate; forming a first doping layer on the first sidewall; covering the first doping layer and a part of a surface of the substrate by a photoresist; forming a second trough structure, which comprises at least a second sidewall, on a part of the substrate which is not covered by the photoresist; removing the photoresist; forming an insulation layer on the substrate, the first trough structure, and the second trough structure; forming a conductive layer on the substrate, the first trough structure, and the second trough structure; and removing parts of the insulation layer and the conductive layer outside the first trough structure and the second trough structure to expose a surface of the first doping layer at the opening of the first trough structure.