True CSP Power MOSFET Bottom-Source LDMOS
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor power device packaging technologies face challenges in reducing source inductance and resistance, particularly in vertical devices, due to the need for bond-wires and large footprints, which increase costs and limit efficiency in high-frequency applications.
Innovation Solution
A true Chip Scale Package (CSP) design with all drain, source, and gate connections located on the front face of the die, utilizing a bottom-source structure where the source region is on the substrate, allowing for distributed connections and reduced inductance, and eliminating the need for bond-wires and extra packaging materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging with bond-wires is used, then electrical connections can be established, but source inductance and resistance increase
Solution Approach 1:
The patent extracts and eliminates the bond-wire from the packaging structure. By configuring the semiconductor substrate itself as the source connection and placing the source electrode directly on the substrate, the invention removes the bond-wire that generates inductance and resistance, achieving direct electrical connection without intermediate components
Solution Approach 2:
The patent merges the substrate and source connection functions. By making the substrate itself the source connection and integrating the source electrode directly onto the substrate surface, the invention combines multiple functions into a single integrated structure, eliminating the need for separate bond-wires and reducing parasitic elements
2Object-generated harmful factors
If substrate is configured as source connection, then source inductance is reduced, but packaging complexity increases
Solution Approach 1:
The patent makes the substrate serve multiple functions: it acts as both the mechanical support and the electrical source connection. This multi-functional design simplifies the overall packaging structure by eliminating the need for separate source connection components, reducing packaging complexity while maintaining low inductance
Solution Approach 2:
The substrate serves itself as the source connection. By configuring the substrate to provide both mechanical support and electrical connection functions, the invention eliminates the need for external source connection components, simplifying the packaging structure and reducing the number of parts required
3Ease of manufacture
If conventional packaging technology is used, then manufacturing is straightforward, but parasitics increase and performance is limited
Solution Approach 1:
The patent inverts the conventional packaging approach by placing the source electrode on the substrate surface rather than requiring back-side connections or top-side bond-wires. This inverted configuration allows for simpler wafer-level processing while eliminating parasitic inductance and resistance associated with traditional packaging methods
4Productivity
If wafer-level processing is used, then manufacturing efficiency increases, but achieving true CSP with low inductance is difficult
Solution Approach 1:
The patent performs the source connection configuration during wafer-level processing before dicing. By pre-configuring the substrate as the source connection and forming source electrodes on the substrate surface during wafer fabrication, the invention achieves true CSP packaging with low inductance through efficient wafer-level manufacturing
Data Source
AI summary
A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate.