Truncated Summation Array for Multi-Divisor Division
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for implementing division operations in integrated circuits are costly and complex, especially when multiple divisors are involved, as they require multiple fixed logic circuits or programmable logic, which increases circuit area and complexity.
Innovation Solution
A method for deriving a hardware representation of a fixed logic circuit that normalizes divisors, forms a truncated summation array, and determines a corrective constant to perform division operations efficiently by discarding less significant columns and rows, allowing for a single circuit to handle multiple divisors and rounding modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple fixed logic circuits are provided for division by different divisors, then division operations for multiple divisors can be performed, but circuit area and complexity increase significantly
Solution Approach 1:
The patent implements a single fixed logic circuit that can perform division operations for multiple different divisors by using a configurable summation array structure. The circuit accepts a divisor selection input that configures the same hardware resources to perform division by any divisor from a predetermined set, eliminating the need for separate dedicated circuits for each divisor while maintaining accurate rounding behavior for each case
Solution Approach 2:
The summation array is divided into multiple configurable sections that can be selectively enabled or disabled based on the chosen divisor. Each section corresponds to terms in the binary expansion of 1/q, and by configuring which sections are active, the same physical circuit implements different division operations with proper rounding for each specific divisor
2Area of stationary object
If a truncated summation array is used to perform division, then circuit area is reduced, but rounding accuracy may be compromised
Solution Approach 1:
The patent pre-calculates and stores the binary expansions of 1/q for multiple different divisors q. These pre-computed values are used to configure the summation array terms, allowing the circuit to achieve accurate rounded results without performing complex runtime calculations. The truncation points are also predetermined based on error analysis, enabling the circuit to achieve faithful rounding with minimal hardware
Solution Approach 2:
The circuit incorporates an error compensation mechanism that adds a corrective constant to the truncated summation result. This corrective term compensates for the truncation error and ensures that the final output satisfies faithful rounding requirements. The corrective constant is predetermined based on the maximum possible truncation error for each divisor configuration
Data Source
Figure 1~8
Figure 2
Figure 3
AI summary
A computer-implemented method for deriving a hardware representation of a fixed logic circuit for performing division of an input x by a divisor selectable from a plurality of divisors, where x is an m-bit integer, the method comprising: normalising each of the plurality of divisors to form a plurality of multipliers; forming a summation array arranged to multiply the input x by any one of the plurality of multipliers; truncating the summation array by discarding all columns less significant than the kth column of the summation array below the position of a binary point, where k=⌈log2m⌉; determining a corrective constant in dependence on the maximum sum of the partial products discarded from the summation array for at least one of the multipliers; and generating a hardware representation of a fixed logic circuit implementing the truncated summation array including the corrective constant.