Trust Domain State Management via Single Instruction Merging
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Solution Overview
Problem
Current trust domain management in processors is inefficient due to the need for serializing individual instructions to save, load, and clear control and debug states, resulting in significant performance overhead during transitions into and out of trust domains.
Innovation Solution
Introduction of decoder and execution circuitry to implement bulk operations through single instructions such as trust domain state enumeration, load, and save & clear instructions, reducing the latency and overhead of these transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual instructions are used to save, load, and clear control and debug states, then trust domain management is achieved, but performance overhead increases significantly
Solution Approach 1:
The patent combines multiple individual instructions (save, load, and clear operations for control and debug states) into a single integrated instruction sequence. This merging reduces the number of separate operations required during trust domain transitions, thereby reducing performance overhead while maintaining the reliability of trust domain management.
Solution Approach 2:
The patent implements preliminary action by pre-saving control and debug states to a data structure before trust domain transitions. This preparation reduces the complexity and overhead of state management during actual transitions, as the states are already organized and ready for efficient loading or clearing when needed.
2Reliability
If multiple individual instructions are executed for state management, then complete state control is achieved, but transition latency increases
Solution Approach 1:
The patent merges multiple state management instructions into a single integrated operation. By combining save, load, and clear operations into unified instruction sequences, the patent reduces the total number of instruction cycles required for trust domain transitions, thereby reducing transition latency while maintaining complete state control.
Solution Approach 2:
The patent performs preliminary actions by pre-organizing control and debug states in a data structure before transitions occur. This preparation allows for faster execution during actual transitions, as the states are already positioned and formatted for efficient access, reducing the time required for state management operations.
Data Source
AI summary
Techniques for implementing instructions for a trust domain implemented by a processor are described. In certain examples, a hardware processor core, that implements a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain with a region of protected memory, includes a debug register; a control register; decoder circuitry to decode a first single instruction into a first decoded instruction, the first single instruction having a field to indicate a data structure to store a control state of a trust domain and a debug state of the trust domain, and an opcode to indicate execution circuitry is to load the control state of the trust domain from the data structure into the control register and load the debug state of the trust domain from the data structure into the debug register; and the execution circuitry to execute the first decoded instruction according to the opcode.