Trusted Core Security Interrupt Isolation With SIDT Routing
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Solution Overview
Problem
Existing computing systems lack effective mechanisms to isolate and secure the processing of security interrupts from normal interrupts, leading to potential security vulnerabilities.
Innovation Solution
Implementing a trusted computing system with a processor containing a trusted core and an isolated memory, coupled with a chipset that includes a security interrupt controller and descriptor table, along with a memory protection configuration to segregate and manage interrupts and memory access for security peripherals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a unified interrupt controller is used for both normal and security interrupts, then device complexity is reduced, but security is compromised due to lack of isolation
Solution Approach 1:
The interrupt controller is segmented into two independent parts: a first interrupt controller for normal interrupts and a second interrupt controller for security interrupts. This segmentation isolates security interrupt processing from normal interrupt processing, preventing unauthorized access while maintaining separate control paths for each interrupt type.
Solution Approach 2:
The security interrupt controller is extracted as a separate entity from the normal interrupt controller. The second interrupt controller is specifically designed to handle only security-related interrupts, removing the security processing function from the unified controller and placing it in a dedicated isolated component.
2Reliability
If isolated memory is provided for trusted computing, then security is improved, but device complexity increases due to additional memory management
Solution Approach 1:
The system memory is segmented into isolated memory regions that are exclusively allocated for trusted computing operations. These isolated memory areas are separated from normal memory spaces, ensuring that security-critical data and code reside in protected regions accessible only through the trusted core.
Solution Approach 2:
The second interrupt controller acts as an intermediary between security peripherals and the trusted core, managing access to isolated memory. This mediator component coordinates security interrupt handling and memory access requests, ensuring proper isolation while simplifying the interface between different security components.
3Reliability
If security peripherals are isolated from normal peripherals, then security is enhanced, but ease of operation decreases due to separate access paths
Solution Approach 1:
Peripherals are segmented into security peripherals and normal peripherals, with each type connected to its dedicated interrupt controller. Security peripherals interface with the second interrupt controller while normal peripherals use the first interrupt controller, creating clear separation while maintaining organized access paths.
Solution Approach 2:
The second interrupt controller serves multiple security-related functions: handling security interrupts from various security peripherals, managing isolated memory access, and coordinating with the trusted core. This multi-functional design consolidates security operations into a single controller, improving ease of operation within the security domain.
Data Source
AI summary
A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.