Trusted Expansion Memory Access for Heterogeneous Compute Nodes

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Solution Overview

Problem

Existing computing systems face challenges with increased coherence traffic and latency due to multiple coherent memory domains, especially in cloud-based edge architectures, leading to inefficiencies in managing coherency across multiple processors and accelerators.

Innovation Solution

A system with dynamic and fine-grained control of coherency using Compute Express Link (CXL) interconnects, allowing for flexible and scalable management of coherent and non-coherent memory domains, enabling per-tenant coherency and quality of service through CXL switches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple coherent memory domains are used to support multiple processors and accelerators, then memory capacity and bandwidth are increased, but coherence traffic and latency increase

Engineering Contradiction:
Improvememory capacityVSAvoidcoherence latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The system segments the coherent memory domain into multiple non-coherent memory domains, each associated with specific compute nodes. This segmentation allows memory to be logically divided while physically shared, reducing unnecessary coherence traffic between nodes that don't require coherent access patterns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically configures memory domains and coherence relationships at runtime based on workload requirements. Memory domains can be created, modified, or deleted as needed, allowing the system to adapt coherence traffic patterns to actual access patterns rather than maintaining static coherent domains for all possible access scenarios.

Inventive Principle:
Principle #15Dynamics

2Productivity

If multiple coherent memory domains are used to enable shared computing and memory, then resource utilization is improved, but system complexity increases

Engineering Contradiction:
Improveshared computing efficiencyVSAvoidcoherency management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system introduces a memory domain configuration mechanism that acts as an intermediary between compute nodes and memory resources. This configuration layer manages the mapping between compute nodes and memory domains, handling the complexity of coherency management abstractedly rather than requiring direct complex coordination between all memory components.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system applies different coherence properties to different memory domains based on local requirements. Rather than enforcing global coherence across all memory access, each memory domain can have its own coherence characteristics tailored to the specific access patterns of associated compute nodes, simplifying the overall coherency management.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250291940A1Apparatus and method for trusted access to expansion memory by multiple potentially heterogeneous compute nodes
Publication Date: 2025.09.18 INTEL CORP
  • US20250291940A1 patent drawing
  • US20250291940A1 patent drawing
  • US20250291940A1 patent drawing

AI summary

Multiple roots of trust are described under a super Root of trust (SROT). One embodiment includes: cores of a host processor; a host processor memory subsystem to provide access to a host processor memory; a home agent to provide access by the cores to the host processor memory subsystem and an expansion memory subsystem, a source address decoder to decode memory requests generated from the plurality of cores to determine whether the memory requests are to be directed to the host processor memory subsystem or the expansion memory subsystem. Host-based security circuitry encrypts and decrypts memory requests directed to the expansion memory subsystem, the host-based security circuitry to perform the encryption and decryption based on a second key stored in a cache maintained by the host-based security circuitry.