Processor Trusted Memory Execution With Hardwired Tripwire Halt
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Solution Overview
Problem
Existing processors face vulnerabilities in securely executing instructions from trusted and untrusted memories, particularly in multi-threaded environments, where unintended or malicious events can cause execution to switch from trusted to untrusted memory, compromising security algorithms.
Innovation Solution
A processor with integrated execution logic, a first flag, and termination circuitry ensures that instructions are initially executed from a trusted memory (ROM) and halts execution if switched to an untrusted memory, using hardwired flags to enforce a 'hard mode' and 'tripwire' mechanisms to prevent unauthorized transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If instructions are executed from untrusted memory (RAM), then flexibility and ease of modification are improved, but security and reliability deteriorate
Solution Approach 1:
The patent segments the execution environment into two distinct modes: hard mode (trusted execution from ROM) and soft mode (untrusted execution from RAM). This segmentation allows the system to simultaneously support both secure execution and flexible modification by isolating them in separate operational contexts. The execution logic can switch between these modes based on the security requirements of the task.
Solution Approach 2:
The patent introduces a tripwire mechanism as an intermediary between the trusted and untrusted execution environments. This tripwire monitors execution transitions and can trigger security responses when unauthorized transitions are detected. It acts as a mediator that enables flexible execution while maintaining security boundaries.
2Adaptability or versatility
If execution switches from trusted memory to untrusted memory, then adaptability is improved, but security and reliability worsen
Solution Approach 1:
The patent implements feedback mechanisms through the tripwire that continuously monitor execution state and provide feedback to the security system. When execution attempts to transition from trusted to untrusted memory, the tripwire detects this change and triggers appropriate security responses. This feedback loop enables the system to adapt execution modes while maintaining security through continuous monitoring and response.
Solution Approach 2:
The patent employs preliminary actions by pre-configuring tripwires and security policies before execution begins. The system establishes trusted execution paths and security boundaries in advance, allowing flexible adaptation during execution while ensuring that security constraints are already in place to prevent unauthorized transitions.
3Device complexity
If a general-purpose microprocessor is used for security algorithms, then device complexity and silicon area are reduced, but security against tampering deteriorates
Solution Approach 1:
The patent applies local quality by creating a localized trusted execution environment within the general-purpose microprocessor. Instead of making the entire processor secure, it establishes a secure zone (hard mode) with specific security properties for executing critical code from ROM, while allowing the rest of the processor to operate with full flexibility for untrusted code from RAM.
Solution Approach 2:
The patent achieves universality by enabling a single general-purpose microprocessor to fulfill multiple roles: it can execute trusted security-critical code from ROM in hard mode, and simultaneously execute untrusted application code from RAM in soft mode. This multi-functionality eliminates the need for separate dedicated security hardware while maintaining both security and flexibility.
4Ease of operation
If RAM is used for security algorithms, then ease of programming and modification is improved, but vulnerability to malicious attacks worsens
Solution Approach 1:
The patent introduces dynamics by allowing the execution environment to change modes between hard mode (secure) and soft mode (flexible). The system can dynamically switch between these states based on the security requirements of the current task, enabling easy programming when in soft mode while maintaining security when switching to hard mode for critical operations.
Solution Approach 2:
The patent applies preliminary anti-action by pre-establishing security measures (tripwires, mode checks) that prevent malicious attacks before they can compromise the system. The tripwire mechanism is configured in advance to detect and respond to unauthorized execution transitions, countering potential attacks before they succeed.
Data Source
AI summary
A processor comprising, in the same integrated circuit or IC package: a first memory comprising one or more memory units, execution logic, a first flag, a second flag, and termination circuitry. The execution logic is arranged so as to always begin by fetching and executing a sequence of instructions from the first memory upon start-up of the processor. The first flag is hardwired to begin as asserted when the processor starts-up, and to be automatically de-asserted when the execution logic switches to executing any instruction of the sequence from any second memory instead of the first memory. The termination circuitry is hardwired to halt the execution the sequence of instructions by the execution logic if the first flag is de-asserted when the second flag is asserted.