TS Clock Signal Generation with Variable Frequency Division
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Solution Overview
Problem
Conventional signal processing devices output TS clock signals with coarse resolution due to limited duty cycle and division modes in parallel and serial clocks, failing to meet the requirements of devices connected to the TS interface, which need higher resolution and lower average frequency TS clock signals corresponding to the TS bit rate.
Innovation Solution
A signal processing device with a valid clock width calculation unit and TS clock signal generation unit that combines clocks with different frequency dividing rates to generate TS clock signals with higher resolution and frequency accuracy, including parallel and serial clock signals, by calculating valid clock widths and adjusting clock signal patterns based on integer and decimal sections of the operating clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a TS clock signal with 50% duty cycle is output in parallel clock mode, then the DVB-CI Plus standard is met, but the resolution of the average frequency becomes coarse
Solution Approach 1:
The patent segments the clock signal generation into multiple independent units: a parallel clock signal generation unit and a serial clock signal generation unit. Each unit can operate with different frequency dividing rates, allowing the system to combine multiple clock signals to achieve fine frequency resolution while maintaining standard compliance through proper duty cycle control in the parallel path.
Solution Approach 2:
The patent dynamically selects and combines clock signals with different frequency dividing rates based on the required TS bit rate. The system can adaptively adjust which clock sources are used and how they are combined, enabling continuous frequency adjustment with high resolution while maintaining the 50% duty cycle requirement for standard compliance.
2Object-affected harmful factors
If limited division modes are prepared in the operating clock for serial clock mode, then noise in receiving RF is reduced, but the resolution of the average frequency of the output TS clock signal becomes coarse
Solution Approach 1:
The patent merges multiple clock signals with different frequency dividing rates to create a composite TS clock signal. By combining clocks from both parallel and serial paths, the system achieves fine frequency resolution that would be impossible with limited division modes alone, while the parallel path maintains the noise-reducing 50% duty cycle characteristic.
Solution Approach 2:
The patent changes the frequency dividing rate parameter of the operating clock to generate multiple clock signals with different frequencies. By varying this parameter across multiple division modes (2x, 3x, 4x, etc.), the system creates a set of clock sources that can be selectively combined to achieve the required high-resolution frequency control.
3Reliability
If only a division at a duty of 50% is performed in the operating clock for parallel clock mode, then the DVB-CI Plus standard is met, but the resolution of the average frequency becomes coarse
Solution Approach 1:
The patent makes the clock generation system multi-functional by creating both parallel and serial clock signal paths that can serve different purposes. The parallel path maintains 50% duty cycle for standard compliance, while the serial path provides additional frequency division options. Together, they provide a universal solution that meets both standard requirements and high-resolution frequency control needs.
Data Source
AI summary
Provided is a signal processing device including: a valid clock width calculation unit configured to calculate a valid clock width corresponding to a bit rate of a valid section in which a transport stream (TS) packet exists; and a TS clock signal generation unit configured to generate, on a basis of the valid clock width calculated by the valid clock width calculation unit, a TS clock signal by combining clocks with different frequency dividing rates.