Through-Semiconductor-Chip Via Failure Detection Using Latching Units
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Solution Overview
Problem
Current semiconductor technologies face challenges in rapidly detecting and effectively repairing failures in through-semiconductor-chip vias, which are time-consuming processes due to the need to test and repair all semiconductor chips when a failure occurs, even if it's isolated to one chip.
Innovation Solution
The implementation of a semiconductor device with latching units assigned to each through-semiconductor-chip via, forming a boundary scan path to sequentially transfer test data, allowing for rapid detection and repair of failures by isolating the faulty via and performing repairs across all connected chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional testing methods are used to detect through-semiconductor-chip via failures, then all semiconductor chips must be tested and repaired even when failure is isolated to one chip, but this results in excessive testing time and reduced productivity
Solution Approach 1:
The patent divides the testing process by assigning a dedicated latching unit to each through-semiconductor-chip via, enabling independent testing of individual vias. This segmentation allows the test system to identify and isolate failures to specific via locations without requiring comprehensive testing of all chips, thereby maintaining high reliability while improving productivity.
Solution Approach 2:
The latching unit serves as an intermediary component between the test data input and the through-semiconductor-chip via. It stores test data and enables selective activation of specific vias for testing, acting as a mediator that allows precise control and isolation of individual via testing, thus avoiding the need to test all chips when only one via may be faulty.
2Measurement precision
If comprehensive testing of all chips is performed to ensure reliable failure detection, then testing completeness is improved, but testing time increases significantly
Solution Approach 1:
The latching units pre-store test data in advance, preparing the testing system before actual via testing begins. This preliminary action allows the system to quickly activate and test specific vias without requiring comprehensive testing of all chips, thereby maintaining precise failure detection while reducing overall testing time.
Solution Approach 2:
The testing system is made dynamic through the latching units, which can selectively activate and deactivate specific via testing based on test requirements. This dynamic control allows the system to adaptively test only the necessary vias, maintaining measurement precision while minimizing time loss by avoiding unnecessary testing of other chips.
Data Source
AI summary
A semiconductor device and a method for driving the same rapidly detect failure of a through-semiconductor-chip via and effectively repairing the failure using a latching unit assigned to each through-semiconductor-chip via. The semiconductor device includes a plurality of semiconductor chips that are stacked, and a plurality of through-semiconductor-chip vias to commonly transfer a signal to the plurality of semiconductor chips, wherein each of the semiconductor chips includes a multiplicity of latching units assigned to the through-semiconductor-chip vias and the multiplicity of latching units of each of the semiconductor chips constructs a boundary scan path including the plurality of through-semiconductor-chip vias to sequentially transfer test data.