TSG Deck Channel Plug Structure for Smaller 3D NAND Die Size
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Solution Overview
Problem
There is a challenge in reducing the die size of 3D memory devices without compromising storage capacity, particularly in 3D NAND memory devices, where conventional methods face difficulties in optimizing area utilization and production costs.
Innovation Solution
The method involves forming a memory device with a channel plug structure that includes an upper and lower plug portion, where the upper plug portion has a narrower width, and a top selective gate (TSG) cut structure, along with a barrier layer and deck structure, to enhance area efficiency and reduce die size while maintaining storage capacity. This is achieved through a series of processes including forming a dielectric-pair stack, a semiconductor layer, and a trench structure, with specific layers and materials like polysilicon and dielectric materials used to create airgaps and separate channel plug structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional methods are used to form 3D memory devices, then storage capacity is maintained, but die size cannot be reduced effectively
Solution Approach 1:
The channel plug structure is divided into an upper plug portion and a lower plug portion with different widths. The upper plug portion has a first width and the lower plug portion has a second width that is greater than the first width. This segmentation allows the channel plug to fit within a reduced die footprint while maintaining sufficient contact area with the channel layer for functional performance.
Solution Approach 2:
The patent transitions from a conventional planar structure to a three-dimensional stacked structure with multiple layers including dielectric layers, channel layers, and control gates arranged vertically. This vertical stacking enables increased storage capacity within a reduced lateral die size by utilizing the third dimension (height) for additional storage elements.
2Area of stationary object
If die size is reduced to improve area utilization, then area utilization improves, but manufacturing complexity increases
Solution Approach 1:
The formation process is segmented into distinct stages: forming the dielectric-pair stack, forming the channel layer, forming the upper and lower plug portions with different widths, and forming control gates at different levels. This segmentation of the manufacturing process enables precise control over the complex three-dimensional structure, making the reduced-die-size device manufacturable through systematic, step-by-step fabrication.
3Area of stationary object
If conventional channel plug structure is used, then manufacturing is simpler, but area utilization is lower
Solution Approach 1:
The channel plug structure employs asymmetric dimensions where the upper plug portion has a first width and the lower plug portion has a second width that is greater than the first width. This asymmetric design optimizes space utilization by having a narrower upper section for routing and connection purposes while maintaining a wider lower section for robust electrical contact with the channel layer, thereby improving area utilization without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced die size along the bit line direction of 3D memory devices, improving area utilization and reducing production costs by effectively forming a memory device with enhanced structural integrity and efficiency.
Implementation Method 1
forming the barrier layer includes performing an oxidation process to convert a portion of the sidewalls of the semiconductor layer exposed by the trench into the barrier layer
Data Source
AI summary
Memory device, memory system, and formation method are provided. The formation method includes providing a dielectric-pair stack containing a channel layer extending there-through, and forming a sacrificial layer in the dielectric-pair stack and in contact with the channel layer; forming a semiconductor layer over the dielectric-pair stack, the semiconductor layer containing a top selective gate (TSG) cut structure; forming a trench through the semiconductor layer to expose the sacrificial layer; forming a barrier layer on sidewalls of the semiconductor layer exposed by the trench; forming a recess by removing the sacrificial layer; and forming a channel plug structure in the trench and the recess.